Feb 2024 – Present · 2 yrs 4 mos · Noida, Uttar Pradesh, India · On-site

Jan 2024 – Present · 2 yrs 5 mos · Noida, Uttar Pradesh, India · On-site

Nov 2020 – Jan 2024 · 3 yrs 2 mos · Noida, Uttar Pradesh, India · On-site

• ~Developed good knowledge on NDM/frame view creation for different technology nodes
• created the guidelines for NDM/frame view creation for older plus newer technology nodes, for seamless consumption by the PNR tool
• ~ Created different custom designs with Auto place and route tool
• methodology involves creation of complete leafcell with auto place and route tool with DRC and LVS clean for final sin-off
• creation of complete IP design with the help of auto place and route tool (for specific type of IPs)
• ~ Methodology to create views for IPs which can be consumed by diagnostics tools for fault analysis and localization of faults inside the IPs
• involves LEF/DEF creation of IPs which is suitable for running FA tools
• ~ RTL2GDS flow to verify different views of IPs
• worked on creation of complete RTL2GDS flow through which all the supported views of IPs verified in-house before shipping to customer
• eliminate any extra surprises for customer while using the provided IP views
• ~ Worked on the inclusion of PRF(placement rule file) for different IPs
• created and used PRF for different IPs during the integration of IPs on the SOC
• faster turn around time in terms of placement of different components/IPs on SOC
• ~ Continuously helping teams for any customer queries/issues related to IP integration, routability, abutment schemes etc.
• ~Developed strong knowledge on automation related to PNR tools to create different methodology for product improvement and reduction of IP development cycle

Oct 2018 – Nov 2020 · 2 yrs 1 mo · Noida, Uttar Pradesh, India · On-site

• ~ Worked on the methodology for abutment of IPs on the SOC design
• Apart from regular abutment of IPs, designed a way through which direct abutment of IPs can be achieved during the placement of the IPs on SOC
• Created in-house validation plan using ICC2/FC to verify the abutment schemes using final sign-off using ICV
• ~Worked on the methodology to reduce the effort during placement lead DRC issues during final sign-off check
• Created and validated a chip integration checker with the use of ICC/FC tool which checks for placement of different components on SOC which leads to DRC at the sign-off

Sep 2017 – Oct 2018 · 1 yr 1 mo · Noida, Uttar Pradesh, India · On-site

• ~ Created and validated ERC methodology for different technology nodes (28nm to 7nm)
• Part of methodology in which using ICV commands created and validated ERC deck , provides fast convergence to resolve any issue related to metal overhangs, poly, diffusion length etc. during IP development
• ~ TCL scripting to find the coupling between different nets inside the IP blocks
• ~ worked on the layout design for different leafcells for different technology nodes(older plus newer)