Avinyash Singh

Software Engineer

Bengaluru, Karnataka, India3 yrs 9 mos experience
Most Likely To Switch

Key Highlights

  • Expert in ASIC design and physical design methodologies.
  • Proficient in using Cadence tools for design verification.
  • Strong foundation in digital electronics and scripting.
Stackforce AI infers this person is a skilled ASIC design engineer with expertise in physical design and verification.

Contact

LinkedIn

Skills

Core Skills

Logic SynthesisPhysical DesignDesign Rule Checking (drc)

Other Skills

GenusInnovusTempusConformalGrepCadence InnovusVirtuoso Layout EditorQuantusPVSScriptingClock Tree SynthesisOn Chip VariationSignal IntegrityFloorplanningPlace & Route

About

● I have always wanted to work in core areas ever since I started my engineering. I look forward to hearing from the experienced people of the domain about the methods and habits to be more effective, hone the skills for proper growth and maintain the right balance in the life.

Experience

3 yrs 9 mos
Total Experience
1 yr 3 mos
Average Tenure
1 yr 4 mos
Current Experience

Texas instruments

Digital Design Engineer - PD

Feb 2025 – Present · 1 yr 4 mos · Bengaluru, Karnataka, India · Hybrid

  • Tools : Genus, Innovus, Tempus, Conformal
Logic SynthesisPhysical DesignGenusInnovusTempusConformal

Synopsys inc

Application Engineer - PD

Mar 2024 – Jan 2025 · 10 mos · Bengaluru, Karnataka, India · Hybrid

Signalchip innovations

PD Engineer

Aug 2022 – Mar 2024 · 1 yr 7 mos · Bengaluru, Karnataka, India · On-site

  • Tools : Cadence Innovus, Virtuoso Layout Editor, Quantus, Tempus, PVS
Design Rule Checking (DRC)GrepCadence InnovusVirtuoso Layout EditorQuantusTempus+1

Education

Rajkiya Engineering College Banda

BTech - Bachelor of Technology — Electrical engineering

Jan 2018 – Jan 2022

Lions School

Intermediate — Science

Jan 2015 – Jan 2017

Lions School

High School

Jan 2014 – Jan 2015

Stackforce found 100+ more professionals with Logic Synthesis & Physical Design

Explore similar profiles based on matching skills and experience

CHANDAN JHA

CHANDAN JHA

Senior Hardware Engineer

at Qualcomm

Bengaluru, India5 yrs 9 mos exp
Physical DesignMicroarchitecture
Akshay Kinake

Akshay Kinake

Staff Signoff Application Engineer

at Synopsys Inc

Bengaluru, India3 yrs 11 mos exp
Full Chip timing signoffSMC 3DIC STATiming ClosurePerformance Optimization
Allen Nguyen

Allen Nguyen

SOC Physical Design Engineer

at Synopsys Inc

Ho Chi Minh City, Vietnam5 yrs 3 mos exp
Physical DesignApplication-Specific Integrated Circuits (ASIC)
Srinath Jeevakumar

Srinath Jeevakumar

Senior Architect

at NVIDIA

Bengaluru, India6 yrs 8 mos exp
Performance VerificationSilicon Bring-upPerformance Analysis
Ashutosh Rao

Ashutosh Rao

R&D Engineer

at Synopsys Inc

Bengaluru, India4 yrs 4 mos exp
Static Timing AnalysisCircuit DesignHardware Security
Madhav Chikodikar

Madhav Chikodikar

Executive Director, R&D - FPGA software

at Synopsys Inc

Bengaluru, India32 yrs 2 mos exp
FPGASoftware Development
Abhijeet Shahapurkar

Abhijeet Shahapurkar

Staff Engineer

at Synopsys Inc

Bengaluru, India4 yrs 5 mos exp
Digital IC DesignPhysical Design
SA

Sumit Arora

Sr. Staff, R&D

at Synopsys Inc

South Delhi, India27 yrs 10 mos exp
EDAProduct Development