Diljith P — Product Manager
I am a Senior Principal Product Engineer with 11 years of experience in advanced VLSI physical design, specializing in RTL-to-GDSII implementation for PPA-critical, high-performance CPU and SoC designs. I have consistently enabled customers to achieve their highest-ever CPU frequencies by driving innovative physical design methodologies focused on PPA and Turnaround Time (TAT). I am passionate about pushing silicon performance boundaries and delivering meaningful, lasting impact through innovation. Key Expertise:- • RTL-to-GDSII Implementation (Flat & Hierarchical) • High-Frequency ARM CPU/SoC Design • PPA Optimization & TAT Reduction • Cadence Innovus, Genus, Tempus; Synopsys ICC2, PrimeTime • Advanced Node Implementation (TSMC / Intel) • Flow Development & Automation (TCL, Perl, Python)
Stackforce AI infers this person is a VLSI Design Expert specializing in high-performance CPU and SoC implementations.
Location: Bengaluru, Karnataka, India
Experience: 10 yrs 11 mos
Skills
- Rtl-to-gdsii Implementation
- Physical Design
- High-frequency Design
Career Highlights
- 11 years in advanced VLSI physical design
- Expert in RTL-to-GDSII implementation
- Proven track record in PPA and TAT optimization
Work Experience
Cadence Design Systems
Sr Principal Product Engineer (1 yr 11 mos)
Principal Product Engineer (2 yrs 10 mos)
Intel Corporation
Component Design Engineer (6 yrs 2 mos)
Education
Master of Technology (M.Tech.) at National Institute of Technology Calicut
Bachelor of Technology (B.Tech.) at Govt. Engineering College Sreekrishnapuram
