Bhawana Jain

CEO

India11 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Extensive experience in solutions engineering management.
Proficient in VLSI and semiconductor design tools.
Strong background in memory characterization and layout verification.

Stackforce AI infers this person is a Semiconductor Engineering Manager with expertise in VLSI design and CAD tools.

Contact

bj.sanu27@gmail.com LinkedIn

Skills

Core Skills

Memory CharacterizationLayout Verification

Other Skills

Evaluation and benchmarking of memory development CAD toolsImprovisation of Memory Characterization FlowValidation of newer tool suggested by vendor companiesEvaluation and improvisation of methodology for post layout challengesParasitic ExtractionMemory scrambling viewsLayout Verification (DRC, LVS)UnixWindowsCadence VirtuosoCadenceliberate_MXStarRCEldoCharacterization

Experience

11 yrs 8 mos

Total Experience

5 yrs 10 mos

Average Tenure

10 yrs 9 mos

Current Experience

Synopsys inc

6 roles

Solutions Engineering Manager

Promoted

May 2026 – Present · 1 mo · On-site

Solutions Engineering Sr Staff

Feb 2025 – Apr 2026 · 1 yr 2 mos · On-site

Solutions Engineering Staff

Feb 2024 – Feb 2025 · 1 yr · On-site

Solutions Engineering Sr II

Promoted

Oct 2021 – Feb 2024 · 2 yrs 4 mos · On-site

Sr CAE

Promoted

Jun 2018 – Nov 2021 · 3 yrs 5 mos · On-site

CAE II

Aug 2015 – Jun 2018 · 2 yrs 10 mos · On-site

Stmicroelectronics

Intern

Jul 2014 – Jun 2015 · 11 mos · Greater Noida

My job is Evaluation and bench marking of memory development CAD tools,
> Improvisation of Memory Characterization Flow
> Bench marking of True spice (ELDO) and Fast spice (XA) simulators for different - different memory compilers
> Validation of newer tool suggested by vendor companies.
> Evaluation and improvisation of methodology for post layout challenges and memory scrambling views
> Parasitic Extraction-simultaneous multiple corner extraction which could bring down
the maintenance cost of netlist and extraction cost to all time low using StarRCXT.
> Memory scrambling views-Understanding of new tool “MASIS” and run the verification test.
> Layout Verification (DRC, LVS)