Prashuk Jain

Director of Engineering

Bengaluru, Karnataka, India13 yrs experience

Highly Stable

Key Highlights

Proven track record in RTL2PD chip implementation.
Expert in driving improvements in chip design processes.
Strong leadership in managing cross-functional teams.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in physical design and methodology.

Contact

Skills

Core Skills

Project ManagementPhysical DesignMethodology

Other Skills

TechnologistsStatic Timing AnalysisUnified Power Format (UPF)Project PlanningDigital DesignsClocksCADSystemVerilogDebuggingFunctional VerificationRTL CodingLogic SynthesisComputer-Aided Design (CAD)Equivalence CheckingArchitectural Design

About

Innovative and results-driven Silicon Methodology Engineer with extensive experience in physical design and Flow development. Proven track record in cutting-edge technology. Adept at identifying inefficiencies and driving improvements in RTL2PD chip implementation processes. Strong leadership & communication skills with a focus on delivering robust smart flows and ensuring a seamless user experience.

Experience

13 yrs

Total Experience

2 yrs 8 mos

Average Tenure

2 yrs 4 mos

Current Experience

Microsoft

2 roles

CAD and Methodology lead - RTL2PD

Jan 2026 – Present · 5 mos · Hybrid

Senior Silicon CAD Engineer

Feb 2024 – Present · 2 yrs 4 mos · Hybrid

Synopsys inc

2 roles

Engineering Manager

Promoted

Feb 2023 – Mar 2024 · 1 yr 1 mo

Led the team of 6 people for design convergence and OOO results for Google g’chips account.
Understand design requirements, code custom APIs and script and propose new enhancements for PPA improvements.
Evaluate tech readiness and and explore design techniques in order to achieve stringent Performance targets

Project ManagementTechnologists

Sr. Application Engineer

Jun 2020 – Feb 2023 · 2 yrs 8 mos

Project migration and tech readiness at cutting edge tech nodes (N3E … ) to achieve clean results, better QOR and PPA targets on critical designs.
Developed Python API's and custom scripts in Tcl for different project requirements.
Owned flow development for different tools FC, PPRTL, Formality, RTLA, DSO, Auto-Macro placement, and issues like FC-PT miscorrelation debug, runtime optimization recipes using native tool commands and code changes.

Physical DesignStatic Timing Analysis

Texas instruments

Senior Digital Design Engineer

May 2018 – Jun 2020 · 2 yrs 1 mo · Greater Bengaluru Area

Worked in HSC-AC (High Speed Converters group) as a Digital design Engineer.
Perform RTL to GDSII implementation on mixed signal design block including Floorplan setup, Placement, CTS, PnR on a multi-clock and multi-voltage design block in Innovus.
Complete end to end ownership of block from synth to signoff checks including STA, power analysis, logical equivalence check and physical verification using industry standard tools.
Owned PLL based clock module synthesis and convergence.
Coded different scripts in TCL/Python to automate various tasks.

Physical DesignUnified Power Format (UPF)

Intel corporation

2 roles

Digital Design Engineer

Apr 2015 – May 2018 · 3 yrs 1 mo

Part of Intel core architecture group (IACG), used to analyse and deploy best of the methodology flow for initial project setup and design convergence.
Enhancing different quality checks for robust design understanding OCV/ AOCV variations. and its impact on path margin. Analysing different PVT corners for correlated timing convergence across corners and outliers. IACG core group award for flow bug.
RTL to Netlist implementation for multiple designs, including end to end convergence from Power/Timing/Layout/Noise Optimization. Involved Latch-Based, RF circuits based designs.

MethodologyTechnologists