Harshit Makwana — Product Manager
Extensive experience in Verilog/SystemVerilog RTL coding, function/performance simulation debugging, and Lint/synthesis/CDC/FV/LEC checks. Proficient in developing Register Transfer Level (RTL) implementations that consistently meet competitive power, performance, and area targets. Skilled in synthesis, timing/power closure, and Field-Programmable Gate Array (FPGA)/silicon bring-up processes. Strong engineering professional with a Master of Technology -M Tech focused on Electronic Systems from the Indian Institute of Technology, Bombay.
Stackforce AI infers this person is a highly skilled engineer in semiconductor design and verification.
Location: Bengaluru, Karnataka, India
Experience: 6 yrs 11 mos
Skills
- Systemverilog
- Synthesis
- Dft
- Formal Verification
- Cdc
- Digital Pll
Career Highlights
- Expert in Verilog/SystemVerilog RTL coding.
- Proficient in power, performance, and area optimization.
- Gold Medalist from IIT Bombay.
Work Experience
Cadence Design Systems
Lead Design Engineer (2 yrs 8 mos)
Samsung Semiconductor
Associate Staff engineer (6 mos)
Senior engineer (Digital IP/Circuit chip design) (2 yrs 8 mos)
Indian Institute of Technology, Bombay
M.Tech Thesis (1 yr 2 mos)
Education
Master of Technology - MTech at Indian Institute of Technology, Bombay
Bachelor’s Degree at L.D. College of Engineering
Diploma at Government Polytechnic, ahmedabad
