Lihui YANG

Associate Consultant

Singapore, Singapore15 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Physical Verification and EDA tools.
Led global QA initiatives for high-quality PDK delivery.
Proven ability to enhance semiconductor design accuracy.

Stackforce AI infers this person is a Semiconductor Engineering Expert with a focus on Physical Verification and EDA solutions.

Contact

Skills

Core Skills

Physical VerificationEda

Other Skills

Layout Versus Schematic (LVS)PerlClean RoomsSimulation SoftwareMulticulturalCMOSMicroelectronicsSemiconductorsPhysicsElectron Beam LithographySiliconNanofabricationIC

About

A collaborative team player and fast learner, who is self-motivated to explore new technologies and innovative solutions with meticulous analysis and has demonstrated strong ability to work under pressure and meet timelines for several concurrent projects either in a team or independently.

Experience

15 yrs 3 mos

Total Experience

3 yrs

Average Tenure

8 yrs 11 mos

Current Experience

Synopsys inc

Senior Application Consultant

Jul 2017 – Present · 8 yrs 11 mos · Singapore

1. Support the sale and adoption of Synopsys products to help customers achieve tangible and lasting performance improvements in the cost.
2. Support Account Managers to provide technical support to ensure customer success.
3. Participate in account planning, working as part of the account team to develop the Synopsys solution to customer problems by bring their understanding of customers' needs and issues.

Layout Versus Schematic (LVS)Physical VerificationEDA

Mentor graphics asia pte. ltd.

Corporate Application Engineer

Feb 2017 – Jul 2017 · 5 mos · Singapore

1. As a Corporate Application Engineer for Calibre product line, help customers solve complex problems in IC circuit and physical verification.
2. Work closely with customers (remote and onsite) to uncover requirements for advanced training and services that increase customer productivity with our tools.

Layout Versus Schematic (LVS)Physical VerificationEDA

Globalfoundries singapore pte. ltd.

Senior Engineer

Mar 2015 – Jan 2017 · 1 yr 10 mos · Singapore

Responsibility
. To review and interpret process design rules for the Process Design Kit development.
· Create and maintain test cases for Process Design Kits / DRC and perform quality assurance checks to ensure error free
Achievement:
1. Participated in 14nm, 22nm, 28nm and 55nm to improve PDK / DRC quality.
2. Independently generated hundreds of High-Voltage DRC quality assurance (QA) patterns
for full coverage of one design rule.
3. Independently lead 55nm QA globally to deliver high quality PDK in time.
4. Self-learnt basic concept about Calibre DRC coding, Calibre DRV usage.

Layout Versus Schematic (LVS)Physical VerificationEDA

Semiconductor manufacturing international corp

Engineer

Mar 2014 – Mar 2015 · 1 yr · Shanghai, China

Achievement:
1.In 28nm PEX runset build-up, enabled Back-End of Line (BEOL) test-key design, and calibrated capacitance extraction within 10% variation compared to silicon data.
2. In one of the CEO main project, named as 013um Mature Technology Enhancement (MTE), built-up conformal conductor structure within 10% variation compared to silicon data which is not supported by EDA embedded tools actually. At the same time, enabled field-solver 3D extraction flow to enhance critical nets PEX accuracy.
3. Participated in 28nm test-key design and WAT test to ensure PEX runset accuracy

Semiconductor manufacturing international corporation

Senior Associated Engineer

Feb 2011 – Mar 2014 · 3 yrs 1 mo · Shanghai

Achievements:
1.. As a key member in 40nm project, explored three more features in PEX runsets which enhanced the richness of PEX runsets three times and less than 10% variation compared to silicon data. Furthermore, contributed in setup for Assura QRC inductance extraction.
2. As a key member in 55nm project, enabled hybrid PEX flow, known as Calibre Connectivity Interface (CCI), which attracts more customers by flexible design flow. Moreover, preserved ideal cell PEX to avoid double extraction when combined with SPICE model.
3. As a key member in one of the CEO project, named as 013um Mature Technology Enhancement (MTE), built-up conformal conductor structure with less than 10% variation compared to silicon data. At the same time, enabled field-solver 3D extraction flow to enhance critical nets PEX accuracy.
4. Enabled back-annotation on PDK platform by Cadence.
5. Participated in 0.13um, 40nm and 28nm test-key design to ensure PEX runset accuracy.
6. Independently build up 0.18um, 0.13um, 90nm and 65nm PEX runset based on custom request.

Physical Verification