POTLA KARTHEEK

CEO

Telangana, India4 yrs 9 mos experience
Highly Stable

Key Highlights

  • Expert in Physical Design tools and methodologies.
  • Recognized for timely delivery and quality of work.
  • Strong team management and problem-solving skills.
Stackforce AI infers this person is a Semiconductor Engineering expert with a focus on Physical Design and Optimization.

Contact

Skills

Core Skills

Optimization TechniquesSemiconductor Engineering

Other Skills

Layout Versus Schematic (LVS)Global Distribution Systems (GDS)ElectronicsEngineeringDesign Rule Checking (DRC)TCLElectronic EngineeringPNRDigital DesignsCommunicationOptimizationComputer-Aided Design (CAD)Power OptimizationRedhawkHardware Engineering

About

A passionate electronics engineer for problems to solve and opportunities to seize. Contributed to Synopsys for almost 3 years as an AE for the Physical Design tools, mainly FC/ICC2 with multiple customer blocks and latest technologies. Always thriving for excellence in every step of the way. A keen observant who enjoys analyzing all aspects of a problem and often comes with out-of-the-box solutions. Constantly recognized for the quality of work delivered in a timely manner. Have good team management skills which were put under test constantly while working with the team. Work area include: -> Specialized in PPA improvement. -> Worked on P&R flow with Fusion compiler on areas such as Floorplanning, Placement & Optimization, CTS and Routing. -> Tech File development and node enablement including node specific PPA elements in flow. -> Highly efficient in scripting and debugging utilities -> Self motived personality and lifelong learner. When not working can be found watching TV series, playing cricket, chit chat with friends and some fun activities. If you ever want to connect fell free to get in touch

Experience

4 yrs 9 mos
Total Experience
4 yrs 9 mos
Average Tenure
4 yrs 9 mos
Current Experience

Synopsys inc

4 roles

R&D Engineer Staff

Feb 2024Present · 2 yrs 4 mos

Optimization TechniquesLayout Versus Schematic (LVS)Global Distribution Systems (GDS)ElectronicsEngineeringDesign Rule Checking (DRC)+9

Solution Engineer Sr I

Jan 2024Jan 2024 · 0 mo

Optimization TechniquesLayout Versus Schematic (LVS)Global Distribution Systems (GDS)ElectronicsEngineeringDesign Rule Checking (DRC)+9

Solution Engineer II

Jun 2023Dec 2023 · 6 mos

Optimization TechniquesLayout Versus Schematic (LVS)Global Distribution Systems (GDS)ElectronicsEngineeringSemiconductor Engineering+9

Application Engineer II

Jun 2021May 2023 · 1 yr 11 mos

Optimization TechniquesGlobal Distribution Systems (GDS)ElectronicsEngineeringSemiconductor EngineeringRedhawk+11

Education

National Institute of Technology Calicut

Master of Technology - MTech — MICROELECTRONICS & VLSI DESIGN

Jan 2019Jan 2021

Chaitanya Bharathi Institute Of Technology

Bachelor of Engineering - BE — Electronics and Communications Engineering

Jan 2013Jan 2017

Stackforce found 100+ more professionals with Optimization Techniques & Semiconductor Engineering

Explore similar profiles based on matching skills and experience