Anshika Mall — Software Engineer
Senior AMS Layout Design Engineer at Synopsys with ~4 years of experience in layout development across advanced technology nodes. Skilled in designing and optimizing a wide range of combinational and sequential cells, including MBFFs and level shifters, with a focus on area efficiency and routing quality. Proficient in industry-standard EDA tools such as Synopsys Custom Compiler, IC Validator, and ICC2, with hands-on expertise in physical verification, PPA optimization, and library release processes. Strong understanding of FinFET and GAA technologies and layout challenges like EM, IR drop, latch-up, and antenna effects.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in layout design and physical verification.
Location: Bengaluru, Karnataka, India
Experience: 3 yrs 2 mos
Skills
- Layout Design
- Physical Design
Career Highlights
- Expert in layout development across advanced technology nodes.
- Proficient in industry-standard EDA tools for physical verification.
- Strong understanding of FinFET and GAA technologies.
Work Experience
Synopsys Inc
Layout Design, Sr Engineer (3 yrs 2 mos)
Post Graduate Engineering Trainee (7 mos)
Education
Master of Technology - MTech at Delhi Technological University (Formerly DCE)
