Anjaneya Medidi

Software Engineer

Bengaluru, Karnataka, India1 yr 8 mos experience

Most Likely To SwitchAI ML Practitioner

Key Highlights

Expertise in VLSI technology and PCIe IP development.
Published research on high throughput circuit design.
Strong foundation in design and manufacturing principles.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and PCIe technologies.

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Skills

Core Skills

DebuggingPcieRtl DesignVerificationResearch SkillsLogic Synthesis

Other Skills

CDCModelSimVerilogSystemVerilogComputer ArchitectureCadence VirtuosoArtificial Intelligence (AI)Xilinx VivadoDigital System DesignDigital Circuit DesignClock GatingSerDesLECLintLogic Design

About

I am a Design Engineer I at Cadence Design Systems, where I contribute to developing cutting-edge VLSI technology. My work on PCIe IP has deepened my expertise in semiconductor technology, and I am passionate about using innovative design strategies to solve complex engineering challenges. I earned my Bachelor of Science in Electronics and Communication Engineering (with a specialization in Design and Manufacturing) from the Indian Institute of Information Technology Design and Manufacturing (IIITDM) Kurnool. This academic background, combined with hands-on industry experience, has equipped me with a robust foundation in design and manufacturing principles. I thrive in collaborative, fast-paced environments and am dedicated to driving advancements in semiconductor solutions. I am always eager to connect with like-minded professionals and explore new opportunities to push the boundaries of technology.

Experience

1 yr 8 mos

Total Experience

10 mos

Average Tenure

1 yr 3 mos

Current Experience

Cadence

2 roles

Design Engineer I

Mar 2025 – Present · 1 yr 3 mos · Bengaluru, Karnataka, India · Hybrid

CDCDebugging

Design Engineering Intern

Feb 2024 – Feb 2025 · 1 yr · Bengaluru, Karnataka, India · Hybrid

Worked on multiple PCIe controller and subsystem customer releases.
Performed quality analysis on PCIe RTL. Quality checks include uniquification, compilation, simulation, lint, CDC, synthesis, and LEC.
Worked on automating a few steps in the release flow to help reduce manual effort.
Achieved a good expertise in analyzing and debugging any issues encountered during the release process.

CDCDebugging

Indian institute of information technology design & manufacturing, kurnool

2 roles

Junior Research Fellow

May 2023 – Oct 2023 · 5 mos · Kurnool, Andhra Pradesh, India · On-site

Worked on IHUB-NTIHAC sponsored research project entitled "Real-time Intelligent System Design for Digital Communication."

Research SkillsComputer Architecture

Research Intern

May 2022 – Sep 2022 · 4 mos · Kurnool, Andhra Pradesh, India

I worked on designing high throughput circuits for digital to analog converters, weighted resistor and resistive ladder type, using Cadence Virtuoso and 90nm CMOS Technology. The generated designs can be configured with a control line to perform different bit operations. The throughput increased by more than 95%. The research work got accepted and published at the International Conference on Recent Advances in Information Technology (RAIT), 2023.

Research SkillsLogic Synthesis

Maven silicon

Advanced VLSI Design and Verification Trainee

May 2023 – Jan 2024 · 8 mos · Bengaluru, Karnataka, India · Hybrid

Trained by industry experts on advanced design and verification technologies, and methodologies such as RTL Design, FPGA Architecture, Advanced Verilog for Verification, SystemVerilog, UVM, Assertion Based Verification, Verification Planning and Management, Code and Functional Coverage, Perl Scripting, and VIP Coding Style.
Worked on two industry level projects: Router 1x3 Design and Verification, and Verification of AHB to APB Bridge.

ModelSimVerilogRTL Design