May 2026 – Present · 1 mo · On-site

Aug 2024 – May 2026 · 1 yr 9 mos · On-site

• Circuit level functional verification of LPDDR5 full-chip netlist with a focus in timing.
• Involved in setting up verification environment, executing full-chip gate level analog simulations (GLS) using Finesim/ Primesim/ SPECTRE across PVTs, performed full chip datapath debugs for failed regression runs and reported timing failure root cause to designers. Tool: Primesim/ SpectreFX
• Developed analog sequence/ pattern for targeted full chip functionality verification.
• Executed low power dynamic circuit checks at full-chip and datapath level for reporting metastability and timing margin violations with respect to setup, hold, recovery and removal timing failures in the design.
• Involved in library characterization activity, writing instance files for cell functionality and timing arcs, generating verilog and timing models for various custom circuits across custom libraries. Tool: SiliconSmart/ Primelib
• Full-chip gate level verilog, RTL netlist and SDF extraction.
• Tool:Primetime, StarRC
• Delevoped python script to automate internal timing check flows with enhanced verification efficiency to reduce repetitive human efforts.