Joan Florez

Product Manager

Santiago, Santiago Metropolitan Region, Chile3 yrs 11 mos experience

Highly Stable

Key Highlights

Promoted three times in four years at Synopsys.
Reduced regression execution time by 90% through automation.
Discovered critical logic defect leading to formal verification mandate.

Stackforce AI infers this person is a Semiconductor Engineer with expertise in EDA tools and formal verification.

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Skills

Core Skills

Eda Tool ValidationFormal VerificationAutomationChip ValidationPcb TestingAnalog Circuit Design

Other Skills

TSMC N2/N3E/N4TCLSynopsys Fusion CompilerFormalityBashMakefileLinuxSynopsys FormalityEDA ToolsSemiconductorsMicroelectronicsPrinted Circuit Board (PCB) DesignFPGA prototypingCadence VirtuosoCMOS 180nm

About

🔧 Senior Electronic Engineer with 4+ years at Synopsys Inc. specializing in EDA tool validation, RTL synthesis, physical design flows, and formal equivalence verification. Promoted 3 times in 4 years. Worked on-site (POV OST) directly with Qualcomm and Intel engineering teams on cutting-edge process nodes — TSMC N2, N3E, N4 and Intel 18A (1278/1276). 📌 Key highlights: Reduced regression execution time by 90% through end-to-end Linux automation (Bash/Makefile/Tcl) for two major clients Discovered a critical bad logic defect in a Qualcomm register bank using Synopsys Formality — a finding so impactful it led to a company-wide OST policy mandating formal verification in all test suites Enabled multiple production-ready Fusion Compiler flow releases for Qualcomm and Intel across advanced nodes Expert in custom physical layout for analog and mixed-signal circuits (CMOS 180nm, Cadence Virtuoso) Holds a recommendation letter from the CIO of Synopsys Chile 🛠 Tools & Technologies: Synopsys Fusion Compiler · Formality · PrimeTime · PrimePower · Cadence Virtuoso · Encounter · Tcl · Bash · Python · Verilog · CHISEL · FPGA (Xilinx) · Git · Linux 🎓 B.Sc. Electronic Engineering — Universidad Industrial de Santander (UIS), specialization in Microelectronics. Thesis: Digital LDO regulator with auto-generated clock in CMOS 180nm. 📬 Open to global opportunities (remote or relocation) in EDA, fabless, and semiconductor companies. Reach me at: joanma.jf@gmail.com

Experience

3 yrs 11 mos

Total Experience

3 yrs 11 mos

Average Tenure

Current Experience

Synopsys inc

3 roles

Application Engineer II

Feb 2023 – Feb 2024 · 1 yr

EDA ToolsSemiconductors

Senior Application Engineer — POV On-Site Testing (OST)

Promoted

Apr 2022 – Mar 2026 · 3 yrs 11 mos

▸ Promoted 3 times in 4 years, advancing to Senior AE managing top-tier accounts (Qualcomm, Intel) on advanced process nodes TSMC N2/N3E/N4 and Intel 18A.
▸ Executed large-scale regression testing for Synopsys Fusion Compiler across Qualcomm and Intel environments, validating tool releases against production-grade multi-block design suites.
▸ Debugged a wide spectrum of critical issues: crashes, stack traces, QoR degradations, timing failures (TNS/WNS/MVP), power (dynamic/leakage), congestion, area, memory, and runtime bottlenecks across full front-end and back-end flows.
▸ Led formal equivalence verification using Synopsys Formality (logic-opto netlists vs. RTL). Uncovered a critical bad logic defect in a Qualcomm register bank — a finding that drove a company-wide mandate for formal verification adoption across all OST teams.
▸ Reduced regression execution time by 90% for two major clients through end-to-end Bash/Makefile/Tcl automation on Linux, eliminating human error entirely.
▸ Resolved client-side setup issues in synthesis flows (app options, NDM, reference libraries, command parameters) and enabled multiple Fusion Compiler production flow releases for Qualcomm and Intel.
▸ Authored detailed STARS bug reports with root cause analysis and reproducers, feeding directly into Synopsys R&D resolution pipeline.
▸ Integrated AI tools into engineering workflows: Synopsys Copilot AI, GitHub Copilot, Claude Code.

TSMC N2/N3E/N4TCLSynopsys Fusion CompilerFormalityBashMakefile+3

Application Engineer I

Apr 2022 – Feb 2023 · 10 mos

MicroelectronicsEDA Tools

Universidad industrial de santander

Lab Lead and Research Engineer - ONCHIP Research Group

May 2018 – Mar 2021 · 2 yrs 10 mos · Bucaramanga · On-site

▸ Served as Lab Chief for the ONCHIP research group, overseeing chip validation and PCB-level testing of RISC-V microcontrollers fabricated in Taiwan (collaboration with SiFive).
▸ Thesis project: Designed a Digital Low Drop-Out Regulator (DLDO) with auto-generated dual-mode clock in CMOS 180nm using Cadence Virtuoso and Encounter — achieving significant dynamic power savings. Built complete custom standard cell library (comparators, NAND, 3-state buffers).
▸ Expert in custom physical layout for analog and mixed-signal circuits: schematic → behavioral simulation (corners, Monte Carlo) → layout → DRC/LVS → parasitic extraction (R/C) → post-layout simulation. Final circuit: ~0.053 mm².
▸ Operated wire bonding machine (30μm Au wire), LPKF CNC (PCB fabrication), cleanroom equipment, oscilloscopes, and network analyzers.

Printed Circuit Board (PCB) DesignFPGA prototypingChip ValidationPCB Testing