Lavanya Mittal — Software Engineer
Physical Design Engineer with hands-on experience in complete RTL-to-GDSII flow, specializing in floorplanning, Clock Tree Synthesis (CTS), routing, and sanity checks for library validation. Skilled in industry-standard EDA tools including Fusion Compiler and ICC2. Proficient in TCL and Shell scripting for automation and flow enhancement. Passionate about VLSI backend design, optimization, and solving complex physical design challenges.
Stackforce AI infers this person is a VLSI Physical Design Engineer with expertise in backend design and automation.
Location: Bengaluru, Karnataka, India
Experience: 1 yr 11 mos
Skills
- Physical Design
Career Highlights
- Expert in RTL-to-GDSII physical design flow.
- Proficient in EDA tools like Fusion Compiler and ICC2.
- Strong background in VLSI backend design and optimization.
Work Experience
Synopsys Inc
ASIC Physical Design Senior Engineer (1 mo)
ASIC Physical Design Engineer (1 yr 10 mos)
Graduate Engineer Intern (6 mos)
VLSI EXPERT Private Limited
Trainee (6 mos)
Education
Bachelor of Technology - BTech at Guru Gobind Singh Indraprastha University
at Doon public school
