Ajay Kumar Chowdhary

Software Engineer

Noida, Uttar Pradesh, India7 yrs experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in SRAM Memory design and characterization.
  • Hands-on experience with advanced technology nodes like 5nm and 3nm.
  • Strong background in both Analog and Digital Circuit Design.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in SRAM and VLSI technologies.

Contact

Skills

Core Skills

Compiler Assembly File (caf) DevelopmentFormal Equivalence VerificationDesign And VerificationBit Cell AnalysisMemory DesignCharacterization

Other Skills

QA for circuit checkRelease related activitiesDesign and Verification of Pseudo Dual Port Register FileLeakage & Power correlationQA for trend checkDesign of leaf cellsMarginingAnalog Circuit DesignDigital Circuit DesignCadence VirtuosoResearchVery-Large-Scale Integration (VLSI)Microsoft OfficePowerPointC

About

Individual enriched with the ability to learn new concepts and technology within a short period. Self-motivated and industrious with a high degree of flexibility, creativity, resourcefulness, commitment, and optimism. • Experience in designing/characterizing/margining of SRAM Memory. •Hands-on experience in advance technology nodes like 5nm and 3nm. •Good understanding of SRAM architecture. • Know how of Single Port, Dual Port and Pseudo Dual Port SRAM. •Bit-cell analysis. •Parasitic modeling of the critical path. •Good knowledge of Analog and Digital Circuit Design •Aware of the flow for designing full-custom integrated circuit (schematic entry, behavioral modeling, circuit simulation, custom layout, DRC/LVS, Parasitic extraction). •Familiarity with Perl/TCL scripting.

Experience

7 yrs
Total Experience
3 yrs 6 mos
Average Tenure
6 yrs 6 mos
Current Experience

Synopsys inc

4 roles

Staff Engineer

Feb 2024Present · 2 yrs 4 mos

R&D Engineer Sr I

Feb 2023Mar 2024 · 1 yr 1 mo

R&D Engineer II

Nov 2020Jan 2023 · 2 yrs 2 mos

  • Compiler Assembly File (CAF) development for different compilers(High Speed and High Density ).
  • Formal equivalence verification using VXL and ESPCV.
  • QA's for circut check.
  • Involved in various release related activities.
Compiler Assembly File (CAF) developmentFormal equivalence verificationQA for circuit checkRelease related activities

R&D Engineer I

Oct 2019Oct 2020 · 1 yr

  • Involved in Design and Verification of Pseudo Dual Port Register File in 5nm technology.
  • Bit Cell Analysis.
  • Leakage & Power correlation and optimization of Compiler.
  • QA for trend check.
  • Involved in various release related activities.
Design and Verification of Pseudo Dual Port Register FileBit Cell AnalysisLeakage & Power correlationQA for trend checkRelease related activitiesDesign and Verification

Insemi technology services pvt. ltd.

Memory Design Engineer Trainee

Apr 2019Oct 2019 · 6 mos · Bangalore

  • During training period, I have gained working experience in the followings:
  • Design of leaf cells( clock generator, Word Line Decoder, Column Decoder I/O path, Self Time Path) for 512X64_M4 Single Port SRAM Memory in 28nm Technology.
  • Characterization:
  • o Cycle time / Access time /mpw clock/ mpw input pins/setup time/hold time
  • o Pin Cap sims
  • o Read power/Write power/Output toggle power/Input pin switching power
  • Calculation of Dynamic Power and Leakage power.
  • Margining:
  • o Read Margin and Tuning the design for optimal sigma
  • o Write Margin and Tuning the design for optimal sigma
  • o Read SNM/Hold SNM/ADM simulations
  • o Internal hold Margins
  • o Pulse width Margins
  • o Overlap/Underlap Margins
Design of leaf cellsCharacterizationMarginingMemory Design

Education

INDIAN INSTITUTE OF ENGINEERING SCIENCE AND TECHNOLOGY, SHIBPUR

Master's degree — VLSI Design

Jan 2017Jan 2019

St. Thomas' College of Engineering & Technology 122

Bachelor of Technology (B.Tech.) — Electronics and Communication Engineering

Jan 2013Jan 2017

Shree Jain Vidyalaya

H.S — Science

Jan 2011Jan 2013

Shree Jain Vidyalaya

Madhyamik

Jan 2011Present

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