Oct 2018 – Jan 2020 · 1 yr 3 mos · Munich, Germany

• Managed multiple Power Management IC programs for Tier-1 customer in Mobile Systems Division
• Program ownership from silicon specification till mass production
• Engineering operations, Resource and budget planing and tracking
• Manage internal engineering teams (Analog and Digital Design, AMS, DMS, Verification, Layout, Silicon validation, Application, Test Engineering, Quality Engineering, Reliability Engineering, Board design, Software, Sample demand planning) across multiple geographies from schedule, deliverables and budget perspective
• Interface with Foundry and Packaging house for silicon manufacturing and assembly
• Report weekly project status to internal executive management as well as customers
• Support Sales and marketing teams for new business opportunities
• Establish strong vendor/Customer relationship

Oct 2016 – Sep 2018 · 1 yr 11 mos · Bengaluru, Karnataka, India

• Managed multiple adjacent market SoC Program/s for Connectivity/Automotive/Wearable
• Responsible for both chip and chipset program management from specification till SoC mass production and sustenance
• Collaborate regularly with other leads to minimize build configurations; improving efficiency and lowering project costs through the R&D process
• Responsible for full product life cycle; leading cross-functional engineering teams through process ensuring product deliverables were met at each phase: design, build, and test.
• Develop comprehensive program plans, detailed schedules, Risk assessments, Risk mitigation, resource requirements, supply-chain strategies, test time reduction and yield enhancement activities.
• Regularly interface with internal/external customers, suppliers, and offshore foundry, assembly and test sites.
• Manage a full portfolio of projects, establish priorities, balance resources, monitor execution and manage customer expectations. Manage the communication with internal teams and senior management

Jul 2014 – Sep 2016 · 2 yrs 2 mos

• Prototype bluetooth sub-system on stand alone FPGA platforms from Altera/Xilinx.
• Develop and enhance FPGA build processes.
• Accelerate pre-si verification.
• Accelerate software and firmware development.
• Early enabling of customer use case application.
• Pre-si validation lead.
• Project management with worldwide verification, design and firmware teams.

Nov 2012 – Jun 2014 · 1 yr 7 mos

• Part of Intel Architecture Group (IAG) responsible for Emulation and Pre-Post Silicon Validation of ATOM line of wireless SOCs.
• Key Responsibilities
• 1. FPGA/Veloce model builds
• 2. Emulation debug (using emulator debug tools)
• 3. Pre-silicon acceleration
• 4. Pre silicon validation planning and execution
• 5. Bug fix validation planning and execution
• 6. Enable worldwide IP and Platform teams for Software developments and lead related debug
• 7. Multisite coordination for project execution
• 8. Risk and mitigation planning and tracking
• 9. Contribute on improving Emulation and validation strategy

Feb 2011 – Oct 2012 · 1 yr 8 mos · Bangalore

• Emulation and pre/post silicon validation lead (Low Power 8/16 bit, 25MHz; Key Responsibilities
• Project Planning for Application Verification and Validation
• FPGA Emulation (Zebu/Palladium/Custom FPGA boards)
• Pre-Silicon Verification
• Pre-Silicon Functional Test case development/enhancements
• Pre-Silicon Validation ("C" and Assembly)
• Post-Silicon Validation ("C" and Assembly)
• Pre/Post Bug Fix Validation
• Boot code and BSL Validation
• Worldwide application engineering Support
• Worldwide Sales and Marketing Support
• Tools and Firmware development Support
• Post-Silicon Bench Characterization Support (Automation - Lab View)

Feb 2010 – Jan 2011 · 11 mos · Hyderabad

• Industry benchmarking for Xilinx ISE and Vivado implementation tools. Create unique design suite catering multiple industry segments like communication, wireless, networking, compute etc that can test tool limits for handling area, pins, clocks, sta, routing etc to find out the bottlenecks. Create weekly reports for improvements to internal development teams. Do evaluations for same designs with competition tools. Do performances report generation for architecture and software development teams. Own benchmarking flow and make sure all the designs are clean with spyglass, timing, p&r and functionality. Help corporate applications engineering team for critical customer issue debugs

Jul 2004 – Jan 2010 · 5 yrs 6 mos · Bengaluru, Karnataka, India

• Post silicon Validation Infrastructure development and Lab automation. Part of worldwide post silicon validation team (Advanced Characterization Engineering). Synthesizable test bench development over FPGA for silicon bringup, debug, analog characterization and lab automation. Complete validation bench modeling and H/W+S/W co-verification in Modelsim.
• Lab View based automation infrastructure development. Design and emulation of numerous synthesizable and completely configurable digital interfaces on Xilinx FPGA based platform. Pre and Post silicon unit level as well as top-level functional validation and analog characterization. Lab characterization bench readiness with automation and debug support. Resource tracking, planning and worldwide lab bench deployment.

Jul 2003 – Jun 2004 · 11 mos

• Hardware FPGA Lead for Nokia's then latest DSLAM (*Digital Subsriber Loop Access Multiplexer) D500. Taken several enhancements to the Digital IPs over different system cards. Managed a team of digital designers to fix the Field issues of Nokia customers.

Apr 2001 – Jul 2003 · 2 yrs 3 mos

• RTL Design
• Functional and Gate level verification
• FPGA/ASIC board design and bring up
• ASIC synthesis
• RTL Linting
• Customer support and product demos.