Rakesh Pandey, Ph.D — Product Engineer
I am Senior Staff R & D at Synopsys. With six + years of experience in this role, I perform research and development in the static timing analysis (STA) domain, a critical aspect of chip design.My core competencies include developing and implementing functionalities for various PrimeTime and distributed-PrimeTime projects, such as Hyperscale/Hypergrid, PTC (GCA), and PTCinPT, using C/C++ and TCL. I have fixed many customer critical issues within the given time deadlines and received the PrimeTime quarterly award for my contributions. In addition, I am the budgeting and hyperscale context area owner of the PrimeTime code, responsible to design cutting edge technology for the chip design.Moreover, my research inclination is towards computer architecture, 3D-ICs etc.
Stackforce AI infers this person is a Senior R&D Engineer in the EDA industry with a focus on static timing analysis.
Location: Bengaluru, Karnataka, India
Experience: 12 yrs 1 mo
Skills
- Static Timing Analysis
- Software Development
- Research And Development (r&d)
Career Highlights
- Over six years in R&D at Synopsys.
- Awarded for critical contributions to PrimeTime.
- Expertise in static timing analysis and chip design.
Work Experience
Synopsys Inc
R and D Engineer, Senior Staff (2 mos)
R & D Engineer Staff (2 yrs 5 mos)
R & D Engineer Senior 2 (5 mos)
R & D Engineer, Senior 1 (3 yrs 8 mos)
BITS Pilani, Hyderabad Campus
Assistant Professor (3 mos)
Indian Institute of Technology, Guwahati
Teaching Assistant, Computer Science and Engineering, IIT Guwahati (5 yrs 10 mos)
Education
Doctor of Philosophy (Ph.D.) at Indian Institute of Technology, Guwahati
Master of Technology (M.Tech.) at Indian Institute of Technology, Guwahati
Bachelor of Technology - BTech at Dr. A.P.J. Abdul Kalam Technical University
High School at Govt Jubilee Inter College, Gorakhpur
