Andrew Rehkopf

CEO

Toronto, Ontario, Canada0 mo experience

Key Highlights

Expert in RTL design and SoC integration.
Proven track record in verification and testing.
Strong background in semiconductor industry projects.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in RTL and verification methodologies.

Contact

Skills

Core Skills

Rtl DesignSoc IntegrationVerificationSystemverilog

Other Skills

TroubleshootingTest Plan DevelopmentFunctional Coverage AnalysisVerification Test PlansUVMRTL DebuggingCoverage AnalysisPython ScriptingPythonUniversal Verification Methodology (UVM)C/C++DebuggingContinuous IntegrationGitMicrosoft Excel

About

Semi-conductor industry specialist with experience designing, verifying, and managing digital IPs

Experience

0 mo

Total Experience

Average Tenure

Current Experience

Synopsys inc

ASIC Digital Design, Staff Engineer

Sep 2024 – Present · 1 yr 9 mos · Greater Toronto Area, Canada · Hybrid

Alphawave semi

Senior Program Manager

Dec 2023 – Sep 2024 · 9 mos · Greater Toronto Area, Canada · Hybrid

Amd

Sr. Silicon Designer

Apr 2022 – Dec 2023 · 1 yr 8 mos · Greater Toronto Area, Canada · Hybrid

Responsible for delivering high-quality RTL from the video codec IP to various SoC repositories on time, and with Lint, DC Elab, Spyglass DFT, CDC and RDC results
Coordinating with managers and RTL designers to ensure all required features are rolled in and verified before delivery to SoC teams
Supporting SoC teams by providing detailed release notes following each release and by troubleshooting any integration issues
Presented test plans based on design specifications to the wider team to identify any potential verification holes as early as possible
Collected functional and line coverage to make test plan updates based on coverage data. Closed coverage to meet and exceed corporate targets

RTL DesignSoC IntegrationTroubleshootingTest Plan DevelopmentFunctional Coverage Analysis

Synopsys inc

ASIC Digital Designer, II

May 2020 – Mar 2022 · 1 yr 10 mos · Greater Toronto Area, Canada · Remote

Working as part of an experienced team verifying 64G, 112G, and 224G PCIe and Ethernet SerDes projects on cutting edge process nodes. Responsibilities include:
Creating and tracking verification test plans
Developing constrained random test benches using SystemVerilog and UVM
Running and debugging RTL, GTECH, and GLS simulations
Collecting and analyzing functional and non-functional coverage
Python, Perl and shell scripting

Verification Test PlansSystemVerilogUVMRTL DebuggingCoverage AnalysisPython Scripting+1

Evertz

Silicon Design Intern

May 2018 – Aug 2019 · 1 yr 3 mos · Burlington, Ontario · On-site

Verified FPGA-based enterprise media routers that used Ethernet and HDMI protocols to route video signals around large corporate and academic campuses.