Omar Abdulrahman

Software Engineer

Canada0 mo experience

Key Highlights

  • Expert in ASIC digital design and verification.
  • Proven automation mindset reducing integration time significantly.
  • Strong background in hardware-software integration.
Stackforce AI infers this person is a Semiconductor and Healthcare software development expert.

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Skills

Core Skills

AsicDigital Circuit DesignAutomationVerificationUniversity TeachingSoftware Development

Other Skills

VerilogSystemVerilogUVMCDCRDCSVAPythonPerlSDLCC++JavaScriptReact.jsPowerAppsVBAAgile Methodologies

About

Computer Engineer specializing in ASIC digital design and verification for high speed interfaces. Currently working on PCIe Gen7 PHY RTL at Synopsys, with hands-on experience in Verilog/SystemVerilog, CDC/RDC, UVM, and SVA under tapeout-driven schedules. Strong design verification crossover skills, automation mindset, and hardware-software integration background. Targeting ASIC Digital Design or Design Verification roles in the SF Bay Area.

Experience

0 mo
Total Experience
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Average Tenure
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Current Experience

Mcmaster university

Teaching Assistant

Jun 2024Dec 2024 · 6 mos · Hamilton, ON · On-site

  • Led weekly lab sessions and guided students through software design, modular programming, and testing practices using C++ and Git-based workflows.
  • Coordinated with the course instructor to address student challenges, ensure consistent evaluation standards, and enhance overall lab efficiency and clarity.
University TeachingSDLCC++

Synopsys inc

ASIC Digital Design and Verification Engineer

Feb 2024Sep 2025 · 1 yr 7 mos · Toronto, ON · Remote

  • Developed Register Transfer Level (RTL) logic for both TX and RX blocks of a PCIe Gen7 SerDes Physical Layer (PHY) using Synopsys VCS and Verdi; resolved critical Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) issues flagged by Spyglass lint and synthesis that enabled on-schedule tapeout milestones.
  • Owned and automated the regeneration of 12 RX wrapper files via Perl-Verilog Generator (PVG), reducing snapshot integration from 3 intern-days to under 4 hours per release cycle and unblocking the entire design team from concurrent RTL, firmware, and testbench changes simultaneously.
  • Authored SystemVerilog Assertions (SVA) for TX register-timing checks and ran Spyglass low-power rule checks on RX logic; boosted functional coverage and caught mis-sequenced configuration events early in simulation.
  • Refactored RX testbench clocking logic to deliver rate-dependent 64 ADC clocks using VCS; uncovered mis-alignments breaking 800+ of 1,500 legacy tests, driving the team decision to rebuild the verification suite from 200 validated core tests outward.
  • Developed 5–10 UVM test sequences and functional coverage components for RX block verification; contributed to bit-true PRBS pattern validation targeting multi-rate Gen1–Gen7 data integrity checks.
  • Built a Python PWL waveform generator for analog PRBS validation, replacing manual per-test waveform construction with a parameterizable tool supporting arbitrary sequence lengths and pattern sizes; adopted by analog and digital teams for cross-domain co-verification.
VerilogSystemVerilogUVMCDCRDCSVA+3

Siemens healthineers

Software Developer

Jun 2021Sep 2023 · 2 yrs 3 mos · Oakville, ON · Hybrid

  • Developed and deployed 10+ internal web apps using JavaScript, React, and PowerApps to digitize access and registration workflows, increasing organizational efficiency.
  • Delivered a credit-management system that reduced processing costs by 37% and approval turnaround by 82% through automated audit trails and a streamlined UI.
  • Automated data pipelines and integrated Power BI dashboards using Python, VBA, and Power Automate, improving data accuracy and enabling real-time KPI tracking.
JavaScriptReact.jsPowerAppsPythonVBASoftware Development

Education

McMaster University

Bachelor of Engineering - BE — Computer Engineering

Sep 2021May 2026

Bishop P. F. Reding Catholic Secondary School

Ontario Secondary School Diploma

Sep 2017Jun 2021

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