Swadhi N

Software Engineer

Kurinjipadi, Tamil Nadu, India4 yrs 9 mos experience

Highly Stable

Key Highlights

Expert in analog layout design with 2+ years of experience.
Proficient in Cadence Virtuoso and layout verification tools.
Strong understanding of CMOS fabrication and design requirements.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in analog layout and verification.

Contact

Skills

Core Skills

Analog LayoutLayout Verification

Other Skills

Working EffectivelyGuardingLVSDRCProblem SolvingTeam ManagementPlanning & SchedulingMetal FabricationVirtual Routing and Forwarding (VRF)Electrical and Instrumentation Engineering (EIE)Critical ThinkingWorking With ClientsLogistics PlanningFixationEquivalence Checking

About

Passionate Analog custom layout engineer. Handled LDO, Amplifier blocks in 5nm . Worked in PLL, RNG,BGR,skew detector ,odac blocks in 5nm,180nm .Got trained in INTEL 7nm and UMC 180nm . 2 + years of experience in Cadence virtuoso Well equppied with icv , calibre and a less on assura Basics of CMOS fabrication Able to deliver blocks with high quality with taking care of all the critical nets and proper shielding and matching . Quick fixing of LVS,DRC within ETA Worked on EMIR , Antenna, density check etc.. Understanding the requirements and changing the layout as per ECO 's with Design Engineer Exploring the bindkeys regularly to optimise my work . Intrested to learn shell scripting

Experience

4 yrs 9 mos

Total Experience

4 yrs

Average Tenure

1 yr 6 mos

Current Experience

Micron technology

2 roles

Engineer

Jan 2025 – Nov 2025 · 10 mos · On-site

Engineer

Dec 2024 – Present · 1 yr 6 mos · On-site

Hcltech

Senior Software Engineer

Sep 2021 – Nov 2025 · 4 yrs 2 mos · Hubli, Karnataka, India

Hcl technologies limited

Designer

Sep 2021 – Aug 2025 · 3 yrs 11 mos

Worked in Intel 5nm, 7m, UMC 180 nm (Training)
Handled blocks from scratch to Production release, which includes Floor plan, Placement, Routing, LVS DRC, other Layout verification checks, Simulation results ECO, RV, Prod release.
Understanding the circuit designer requirement with handoff.
Handled blocks includes LDO, PLL, TX, eye monitor, vrefgen, DIV
Worked with Israel, Indian clients.
Expertise in LVS debugging, base, metal drc clean up with DRM.
Ensured high speed signal, clock nets to be least coupled or same coupling.
Matching, shielding devices to cross talk and noises.
Ensuring the estimated area even after ECO ’s.
Ensuring layouts with De-cap in empty places.
Ensuring low resistance path for high current net.
Ensuring the dummy check to facilitate proper matching.
Expertise in virtuoso layout L, XL, MXL, EXL
Expertise and exploring in bind keys to ease of work Ex cloning, modgen.
Ensuring symmetrical routing for devices with matching.
Expertise in Antenna fixes, EMIR fixes (RV fixes).
Ensuring proper Guarding, tap cells to prevent latch up effect.
Ensuring adequate power grids for various powers in the blocks.