Jaewon Jung — Software Engineer
Motivated Physical Design Engineer with 3+ years of hands-on experience in SoC and HBM design, covering full back-end flow from netlist to tape-out across deep sub-micron nodes. - Solid background in timing closure, clock/power distribution, and layout verification using Synopsys tool chain (Fusion Compiler / IC Compiler II / Primetime / StarRC / IC Validator) - Experience in deep submicron process technology nodes : Samsung Foundry 8nm, 5nm, 4nm & TSMC 3nm - Track record of working closely with engineering teams across multiple countries and time zones, with a working style built around clear communication and technical ownership.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and SoC methodologies.
Experience: 3 yrs 4 mos
Skills
- Physical Design
- Semiconductor
Career Highlights
- 3+ years of experience in SoC and HBM design
- Expertise in timing closure and layout verification
- Strong communication skills across global teams
Work Experience
Synopsys Inc
Application Engineer (3 yrs 4 mos)
Education
Bachelor's degree at Ewha Womans University 이화여자대학교
Visiting Student at Marburg University
