Ractim Chakraborty

Software Engineer

Bengaluru, Karnataka, India15 yrs 6 mos experience

Highly Stable

Key Highlights

Over 8 years of experience in software development.
Expertise in runtime optimization and compiler design.
Proven track record of enhancing performance in EDA tools.

Stackforce AI infers this person is a specialist in EDA with a focus on compiler design and performance optimization.

Contact

Skills

Core Skills

Runtime OptimizationCompiler Design

Other Skills

Statistical FunctionsMathematical OperatorsParallel Memory ModelVCS CompilerRuntime Memory OptimizationVCSSystem VerilogAssertion CoverageDavinciCompile Time OptimizationDebugging SupportVerilogDebuggingCVHDL

About

I am a curious person who love to learn new and exciting things and try to apply and change. I have been with Software development as a professional for 8+ years now. After passing out from Jadavpur University in Computer Science and Engineering I started my career with Synopsys , EDA domain and worked on Verilog Simulator. I worked on different projects starting from compile time and runtime optimizations, hardwire simulation and also making Davinci tool till productization and helping it getting integrated with existing Synopsys simulator. Moreover I have been part of different optimizations which can be used by customers to speed up their designs. Specialties : Designing and architecting softwares , Algorithms and Data Structures, Compiler Design

Experience

15 yrs 6 mos

Total Experience

15 yrs 6 mos

Average Tenure

15 yrs 6 mos

Current Experience

Synopsys inc

6 roles

Principal Engineer

Promoted

Jun 2022 – Present · 4 yrs

Will work in Performance Team (Both Compile and Runtime)

Staff Research and Development Engineer

Jan 2021 – May 2022 · 1 yr 4 mos

Worked in the following things ->
Runtime Memory Reduction for Better Performance

Senior Research and Development Engineer II

Jun 2017 – Dec 2020 · 3 yrs 6 mos

Worked in the following things ->
Runtime Optimization which was required for AMAZON eval.
Implementation of some Statistical Functions as per LRM
Runtime Optimization of Mathematical Operators to handle big Integers.
Working on parallel memory model for better runtime memory in VCS compiler.

Senior Research And Development Engineer I

Promoted

Jul 2014 – May 2017 · 2 yrs 10 mos

Worked in the following things ->
Standard Runtime memory optimization in VCS leading to good runtime speedup.
Rearchitecting VCS implementation of a System Verilog construct.
Quick implementation to bring good runtime speedup in SAMSUNG eval.
The knowledge I gained is handling of Big projects and finding ideas from EVALS

Research And Development Engineer II

Jul 2012 – Jun 2014 · 1 yr 11 mos

Worked in the following things ->
Implementing Assertion Coverage in Davinci Flow(Davinci is a coverage convergence tool)
Implementing String Based Equation Propagation From Compile time till Runtime in Davinci.
Integration of Certitude With Davinci tool for helping customers in quick code-coverage.
Compile time Optimization which led to 2-5x speedup in most gate-level Designs, work needed from compile time till runtime for full Debugging support for customers wrt to this optimization.
Runtime support to View Signal Equations without recompilation in Davinci.
The knowledge I gained is handling of Big projects not only from scratch BUT also sometimes from the middle.

Research And Development Engineer I

Jul 2010 – Jun 2012 · 1 yr 11 mos

Worked in the following things ->
Supporting 2 new constructs specified from Verilog Language Reference Manual(LRM) in VCS
Integration of Davinci with Synopsys' Simulator(VCS)
Supporting few more new constructs from Verilog LRM in Davinci front and backend Engine.
Creating framework for proper error/warning message at runtime Davinci Engine.
Quick compile time change which brought ~1.5x speedup at runtime in SAMSUNG design.
The knowledge I gained is handling of Large Code, Debugging issues and also if required give a quick prototype to help in customer evals.