Tarun Gupta — Software Engineer
DFT Engineer in Semiconductor Design with an experience of 4.5+ years. I have worked on: -Scan Insertion and Architecture -Pattern Generation and Retargeting -Coverage Analysis, DRC Analysis and Debug -Timing and No-timing Pattern Simulation -RTL SSN and EDT insertion I have worked on tile-level, IP-level and currently working at Core-level for CPU. I am familiar with DFT tools from -Synopsys (DC/FC Compiler, TMAX, VCS and Verdi) -Tessent (FastScan and TestKompress) -Cadence (Genus and Xcelium) I am keen to explore on end-to-end DFT implementation for complex SoC/IP designs, working on design-level to post-silicon. My other interests include graphic design, business development and e-commerce.
Stackforce AI infers this person is a DFT Engineer specializing in semiconductor design and testing.
Location: Bengaluru, Karnataka, India
Experience: 7 yrs 8 mos
Skills
- Asic Dft
- Dft
Career Highlights
- 4.5+ years in DFT for semiconductor design.
- Expertise in ASIC DFT and pattern generation.
- Proficient with leading DFT tools and methodologies.
Work Experience
Samsung Semiconductor
Associate Staff Engineer, DFT (1 yr 9 mos)
Synopsys Inc
Engineer, ASIC DFT (1 yr 3 mos)
Synapse Design Inc.
Engineer, ASIC DFT (1 yr 9 mos)
E-Cell, IIIT Dharwad
Club Head (2 yrs 11 mos)
Education
Bachelor of Technology - BTech at Indian Institute of Information Technology Dharwad
Intermediate at St. Joseph's Senior Secondary School Kanpur
