Jit Banerjee

Software Engineer

Kolkata, West Bengal, India1 yr 11 mos experience

Key Highlights

  • Hands-on experience in RTL-to-GDSII flow.
  • Proficient in Synopsys tools for backend IC design.
  • Strong foundation in digital and analog design methodologies.
Stackforce AI infers this person is a Backend IC Design Engineer with expertise in VLSI and Physical Design.

Contact

LinkedIn

Skills

Core Skills

Physical DesignApplication EngineeringDebuggingTeaching

Other Skills

Fusion CompilerICC2RTL to GDSPrime timePrime powerPNRLinuxVery-Large-Scale Integration (VLSI)Analytical SkillsSystem on a Chip (SoC)Object-Oriented Programming (OOP)CTCProblem SolvingPython (Programming Language)Gate Level Simulation

About

Physical Design Engineer Intern with hands-on experience as an intern, working on RTL-to-GDSII flow using Synopsys tools like IC Compiler II (ICC2), and Fusion Compiler. Passionate about deepening my expertise in backend IC design, including floorplanning, placement & routing, static timing analysis. Seeking a full-time opportunity to apply and expand my skills in high-performance chip implementation and optimization.

Experience

1 yr 11 mos
Total Experience
1 yr
Average Tenure
11 mos
Current Experience

Synopsys inc

2 roles

Senior Engineer

Jul 2025 – Present · 11 mos · On-site

  • Application Engineering Physical Design
Fusion CompilerICC2Physical DesignApplication Engineering

Engineer Intern (Physical Design)

May 2024 – Jun 2025 · 1 yr 1 mo · On-site

ICC2DebuggingPhysical Design

National institute of technology calicut

Teaching Assistant

Aug 2023 – Aug 2024 · 1 yr · Kerala, India

DebuggingRTL to GDSTeaching

Education

National Institute of Technology Calicut

Master of Technology - MTech — Telecommunication

Aug 2022 – Jul 2024

Academy of Technology

Bachelor of Technology - BTech

Aug 2011 – Jul 2015

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