Kavitha Radhakumar

CTO

Australia12 yrs 8 mos experience

AI EnabledHighly Stable

Key Highlights

10 years of experience in telecom systems engineering.
Expert in applying ML techniques for wireless communications.
Proficient in algorithm design for 4G/5G products.

Stackforce AI infers this person is a Telecommunications Engineer with a strong focus on Machine Learning applications.

Contact

Skills

Core Skills

Artificial Intelligence (ai)Electrical EngineeringAlgorithms

Other Skills

2GMLflowAirflowGitBitbucketJenkinsFastAPIData EngineeringStatistical ModelingData ScienceMLOpsLarge Language Models (LLM)TensorFlowDeep LearningSoftware Development

About

Machine Learning–driven Telecom Engineer with 10 years of experience in systems engineering. Skilled in applying ML techniques for wireless communications, including signal classification, channel estimation, and performance optimization. Experienced in algorithm design, development, and testing of demodulators and test base stations for 4G/5G products. Currently working as a 5G L1 developer for ORAN-DU at Radisys, with a focus on integrating AI/ML into next-generation telecom solutions.

Experience

12 yrs 8 mos

Total Experience

4 yrs

Average Tenure

7 mos

Current Experience

Wesfarmers health

Technical Architect- AI&ST

Nov 2025 – Present · 7 mos · Melbourne, Victoria, Australia · On-site

Radisys corporation

Staff Engineer

Aug 2022 – Oct 2025 · 3 yrs 2 mos

Artificial Intelligence (AI)Electrical Engineering

Qualcomm

3 roles

Senior Lead Engineer

Nov 2020 – Aug 2022 · 1 yr 9 mos

Electrical Engineering2G

Senior Engineer

Promoted

Nov 2017 – Nov 2020 · 3 yrs

Algorithms

Engineer

Jul 2015 – Nov 2017 · 2 yrs 4 mos

I am part of Qualcomm India's corporate R&D team and responsible for the analysis and testing of demodulator back end blocks and clock plans for a family of UMTS chipsets. I also work on optimizing & analyzing the RxFE path for supporting the ADC rates for various techs.

Algorithms

Iisc

student

Aug 2013 – Jun 2015 · 1 yr 10 mos

ME student telecommunication

Electrical EngineeringAlgorithms

Broadcom

Intern at IC design division

May 2012 – Jul 2012 · 2 mos · Bangalore

I worked on techniques to reduce delay in high frequency interfaces which included verilog simulation, RTL synthesis. I worked on chip design and timing issues .