Ashish Agrawal — Software Engineer
10+ years of experience in C/C++/Algorithms and Data Structures in Mentor Graphics. Developed & enhanced various key modules of FPGA synthesis and Schematic Generation engine which includes active association with requirement gathering, design & development, testing, automation and effective implementation. Demonstrated high degree of thought leadership and productized next generation innovative solutions for critical customer applications & requirements. Co-authored two IEEE publications & won Best Paper Award in IEEE EWDTS’08, also presented a paper in 53rd IEEE International Midwest Symposium.
Stackforce AI infers this person is a highly experienced EDA engineer with expertise in FPGA development and algorithm design.
Location: Noida, Uttar Pradesh, India
Experience: 18 yrs 10 mos
Skills
- C++
- Fpga
Career Highlights
- 10+ years of experience in C/C++ and algorithms.
- Co-authored two IEEE publications and won Best Paper Award.
- Demonstrated thought leadership in innovative solutions.
Work Experience
Synopsys Inc
Principal Engineer (2 yrs 4 mos)
R&D Engineer, Sr Staff at Synopsys (1 yr)
RnD Staff Engineer (5 yrs)
Mentor Graphics
Consulting Member Of Technical Staff (10 yrs 6 mos)
Education
Bachelor of Technology - BTech at Indian Institute of Technology, Roorkee
