V

Vijaya Lavanya Devika Adabala

Software Engineer

Nuzvid, Andhra Pradesh, India2 yrs experience

Key Highlights

  • Expert in RTL Design and Digital Circuit Design.
  • Proficient in managing complex protocols like CXL and PCIE.
  • Strong analytical and problem-solving skills.
Stackforce AI infers this person is a Digital Design Engineer with expertise in ASIC and high-speed protocols.

Contact

LinkedIn

Skills

Core Skills

Rtl DesignDigital Circuit Design

Other Skills

Synopsys toolsMicro ArchitectureAnalytical SkillsProblem SolvingC++Logic GatesSystemVerilogVerilogLogic DesignElectronic CircuitsCode CoverageCircuit DesignCMOSApplication-Specific Integrated Circuits (ASIC)Communication skills

About

Digital design engineer at Ceremorphic technologies private limited. Working on CXL mem protocol,PCIE Transaction layer and IDE for CXL and PCIE. and have Potential to work with excellent time management.

Experience

2 yrs
Total Experience
2 yrs
Average Tenure
2 yrs
Current Experience

Ceremorphic, inc.

Digital Design Engineer

Jun 2024 – Present · 2 yrs · Hyderabad, Telangana, India · On-site

Synopsys toolsMicro ArchitectureRTL DesignDigital Circuit Design

Education

RAJIV GANDHI UNIVERSITY OF KNOWLEDGE TECHNOLOGIES, NUZVID

Bachelor of Technology - BTech — Electronics and communication

Jul 2020 – May 2024

RAJIV GANDHI UNIVERSITY OF KNOWLEDGE TECHNOLOGIES, NUZVID

Pre University course — Mpc

May 2018 – Jun 2020

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