BOODALA VENUGOPAL REDDY — Software Engineer

I am a Design Verification Engineer with 3+ years of experience in ASIC and SoC verification, specializing in IP- and subsystem-level verification using SystemVerilog and UVM. I have strong hands-on expertise in building reusable and scalable UVM environments, developing constrained-random test scenarios, functional coverage models, and SystemVerilog Assertions (SVA) to ensure robust verification and early bug detection. My experience includes thorough verification of AMBA protocols such as APB, AHB, and AXI, covering register-level validation, integration testing, and protocol compliance. I have worked extensively on peripherals like DMA, PIT, PWM, and WDT, validating read/write flows, programming modes, interrupt handling, and developing dedicated PWM checkers. I am proficient in UVM Register Abstraction Layer (RAL) and experienced in RTL, GLS, and UPF-related debugging. I regularly manage and analyze regressions using vManager and drive coverage closure using Cadence Xcelium and IMC. I enjoy deep debugging, improving verification quality, and contributing to reliable, high-quality silicon. Skills: 1.Verilog HDL. 2.System Verilog (hand on experience in environment development) 3.UVM(Methodology), Assertion-Based Verification (immediate,Deferred, Concurrent SVA) 4.Protocola:AMBA(AXI,AHB,APB),SPI,I2C,UART,I2S. 5.Advanced digital design, 6.ASIC (Application Specific Integrated Circuit) Design Flow. 7.C-Programming, Python. 8.Xilinx, 9.Intel Quartus Prime, 10.Good in Linux Commands. EDA Tools:1.Cadence xcelium 2.vManager(Vericium Manager) 3.Simvision 4.IMC FLOWS: RTL Simulation, Gate-Level-Simulation(Zero/Unit Delay, SDF), UPF, Emulation (palladium,ZeBu) Version control & Environment: Git, Linux, gvim Achievements 1.Awarded with "Karnataka State Level ISTE best student chapter awarded) 1. Member of ISTE Student Co-ordinators 2. Awarded with "PRATIBHA AWARD"from CM of Andhrapradesh for excellence in academics. 2.Won District Level Kabbadi Trophy.

Stackforce AI infers this person is a Design Verification Engineer specializing in ASIC and SoC verification.

Location: Bengaluru, Karnataka, India

Experience: 3 yrs 6 mos