G

Gopisetti Venkatesh

Software Engineer

Andhra Pradesh, India6 yrs 10 mos experience
Highly Stable

Key Highlights

  • 4.5 years in Post Silicon Validation.
  • Expert in debugging and validation plans.
  • Strong background in x86 architecture.
Stackforce AI infers this person is a Post Silicon Validation Engineer with expertise in semiconductor validation.

Contact

LinkedIn

Skills

Core Skills

Post Silicon ValidationDebugging

Other Skills

Validation Plansx86 ArchitectureVerilogProcessorsIntegrated Circuits (IC)Very-Large-Scale Integration (VLSI)C (Programming Language)Shell Scripting

About

I have close to 4.5 years of experience in Post Silicon Validation. Skilled in developing work bench for validation and competent with debugging skills. I have good background in x86 architecture and debug. I have worked in validating the memory clusters in CPU and was responsible in writing Validation plans and finding bugs and root causing them.

Experience

6 yrs 10 mos
Total Experience
2 yrs 5 mos
Average Tenure
1 yr 11 mos
Current Experience

Amd

Sr. Silicon Design Engineer

Jul 2024 – Present · 1 yr 11 mos · Bengaluru, Karnataka, India · On-site

Intel corporation

Post Silicon Validation Engineer

Nov 2020 – Jul 2024 · 3 yrs 8 mos · Bengaluru, Karnataka, India

Post Silicon ValidationDebuggingValidation Plansx86 Architecture

Marvell semiconductor

2 roles

Associate Design Validation engineer

Promoted

Aug 2019 – Nov 2020 · 1 yr 3 mos

Associate Design Verification Engineer

Jul 2019 – Aug 2019 · 1 mo

Education

National Institute of Technology, Tiruchirappalli

Bachelor's degree

Jan 2015 – Jan 2019

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