Chandrakant Ratna 🇮🇳 — Software Engineer
Senior Application Engineer at Synopsys with 3+ years supporting standard cell library deliverables (Liberty, LEF, Netlist, AOCV/POCV/SPOCV, NDM, Verilog, MIS, MTBF, TRF, APL Models, TF, TLUPlus) across mature-to-advanced foundry nodes — GF 22FDX/+, TSMC 22 to 2nm, Samsung 4LPP/8LPU. Hands-on with the Synopsys signoff stack: PrimeTime, PrimeTime SI, Design Compiler, IC Compiler II, PrimePower. Currently exploring opportunities in Static Timing Analysis (STA Signoff) where I can apply deep library-internal knowledge to production timing closure.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in Static Timing Analysis and standard cell libraries.
Location: Bengaluru, Karnataka, India
Experience: 4 yrs 4 mos
Skills
- Static Timing Analysis
- Standard Cell Library
- Very-large-scale Integration (vlsi)
Career Highlights
- 3+ years in standard cell library deliverables.
- Hands-on experience with Synopsys signoff stack.
- Exploring opportunities in Static Timing Analysis.
Work Experience
Synopsys Inc
Senior Application Engineer (1 yr 5 mos)
Application Engineer (2 yrs 5 mos)
OpenFive
IP Engineering Intern (6 mos)
National Institute of Technology Calicut
Teaching Assistant (5 mos)
Education
Master of Technology - M.Tech at National Institute of Technology Calicut
Bachelor of Technology - B.Tech at Madan Mohan Malaviya University of Technology
