Abhimanyu Kumar

Product Engineer

Bengaluru, Karnataka, India2 yrs 6 mos experience
Highly Stable

Key Highlights

  • Expert in advanced node technologies: TSMC 5nm and 2nm.
  • Proficient in physical verification and EM/IR reliability analysis.
  • Strong background in analog layout design for complex systems.
Stackforce AI infers this person is a Semiconductor and IoT specialist with expertise in analog and mixed-signal design.

Contact

Skills

Core Skills

Very-large-scale Integration (vlsi)Analog Layout Design

Other Skills

Design Rule Checking (DRC)Cadence VirtuosoAssuraInternet of Things (IoT)Electrostatic Discharge (ESD)Microsoft ExcelDigital ElectronicsAnalog ElectronicsFloorplanningCadence SoftwareAnalog SemiconductorsSemiconductor DeviceLayout Versus Schematic (LVS)CMOSStandard Cell

About

Analog & Mixed-Signal Layout Engineer at Synopsys with hands-on experience in TSMC 5nm and 2nm technologies, focused on delivering high-performance, silicon-accurate layouts for complex SerDes systems. I specialize in translating circuit intent into robust physical design while ensuring reliability, matching, and manufacturability at advanced nodes. With strong exposure to receiver and transmitter blocks, I work closely with cross-functional teams to optimize layout quality, improve design efficiency, and meet stringent physical verification and EM/IR requirements. Core Expertise & Impact: Advanced node experience: TSMC 5nm & 2nm (deep submicron challenges, LDE awareness) Worked on critical blocks: Rx_Bias, Rx_AFE, Tx_Driver (TDC, VCM, Driver units) Strong in Physical Verification (DRC/LVS signoff mindset) and EM/IR reliability analysis Expertise in matching techniques, common centroid, interdigitation, dummy strategies Deep understanding of layout-dependent effects (WPE, STI stress, antenna, spacing effects) Skilled in Cadence Virtuoso, Synopsys Custom Compiler, ICV, Assura Experience in floorplanning, hierarchical layout, and performance-driven optimization Solid foundation in analog blocks: Op-Amps, Bandgap Reference, Level Shifters, Standard Cells I am particularly interested in opportunities involving SerDes, high-speed interfaces, and advanced AMS design, where precision layout and deep technology understanding directly impact silicon performance.

Experience

2 yrs 6 mos
Total Experience
2 yrs 6 mos
Average Tenure
2 yrs 6 mos
Current Experience

Synopsys inc

A & M S Layout Design Engineer

Dec 2023Present · 2 yrs 6 mos · Bengaluru, Karnataka, India · Hybrid

Very-Large-Scale Integration (VLSI)Design Rule Checking (DRC)

Takshila institute of vlsi technologies

Analog Layout Trainee

Jun 2023Nov 2023 · 5 mos · Bengaluru, Karnataka, India · On-site

  • Analog Layout Design Trainee.
  • Layout Tools: Cadence Virtuoso L, XL
  • Verification Tool: Assura
  • Technologies: gpdk45nm and gpdk90nm
  • Blocks worked on:- Standard Cells(gpdk45nm)
  • Level Shifters, Op-Amp, BGR, LDO, ADC(Gpdk90nm)
Design Rule Checking (DRC)Analog layout designCadence VirtuosoAssura

Nano robotics embed technologies

Project Intern

Aug 2022Sep 2022 · 1 mo · Bengaluru, Karnataka, India · On-site

  • Home Automation System Using IOT
Internet of Things (IoT)

Education

Visvesvaraya Technological University

Bachelor of Engineering - BE — Electrical and Electronics Engineering

Jan 2019Jan 2023

Gyan Niketan

Senior Secondary — PCM

Jun 2017Apr 2019

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