Abhimanyu Kumar — Product Engineer
Analog & Mixed-Signal Layout Engineer at Synopsys with hands-on experience in TSMC 5nm and 2nm technologies, focused on delivering high-performance, silicon-accurate layouts for complex SerDes systems. I specialize in translating circuit intent into robust physical design while ensuring reliability, matching, and manufacturability at advanced nodes. With strong exposure to receiver and transmitter blocks, I work closely with cross-functional teams to optimize layout quality, improve design efficiency, and meet stringent physical verification and EM/IR requirements. Core Expertise & Impact: Advanced node experience: TSMC 5nm & 2nm (deep submicron challenges, LDE awareness) Worked on critical blocks: Rx_Bias, Rx_AFE, Tx_Driver (TDC, VCM, Driver units) Strong in Physical Verification (DRC/LVS signoff mindset) and EM/IR reliability analysis Expertise in matching techniques, common centroid, interdigitation, dummy strategies Deep understanding of layout-dependent effects (WPE, STI stress, antenna, spacing effects) Skilled in Cadence Virtuoso, Synopsys Custom Compiler, ICV, Assura Experience in floorplanning, hierarchical layout, and performance-driven optimization Solid foundation in analog blocks: Op-Amps, Bandgap Reference, Level Shifters, Standard Cells I am particularly interested in opportunities involving SerDes, high-speed interfaces, and advanced AMS design, where precision layout and deep technology understanding directly impact silicon performance.
Stackforce AI infers this person is a Semiconductor and IoT specialist with expertise in analog and mixed-signal design.
Location: Bengaluru, Karnataka, India
Experience: 2 yrs 6 mos
Skills
- Very-large-scale Integration (vlsi)
- Analog Layout Design
Career Highlights
- Expert in advanced node technologies: TSMC 5nm and 2nm.
- Proficient in physical verification and EM/IR reliability analysis.
- Strong background in analog layout design for complex systems.
Work Experience
Synopsys Inc
A & M S Layout Design Engineer (2 yrs 6 mos)
Takshila Institute of VLSI Technologies
Analog Layout Trainee (5 mos)
Nano Robotics Embed Technologies
Project Intern (1 mo)
Education
Bachelor of Engineering - BE at Visvesvaraya Technological University
Senior Secondary at Gyan Niketan