RAJESH CHEERA — Product Manager

Analog Layout Engineer with 6+ years of experience in the VLSI industry, specializing in high-performance analog and mixed-signal physical design. Experienced in delivering block-level to full IP-level layouts from floorplanning through final tape-out and sign-off. Strong expertise in precision layout methodologies including common centroid, interdigitation, symmetry optimization, shielding, and parasitic-aware design techniques. Hands-on exposure across advanced and mature technology nodes, ensuring performance-driven and silicon-accurate implementations. Well-versed in complete physical verification flows such as DRC, LVS, ERC, and post-layout validation. Proficient in Cadence Virtuoso and Synopsys Custom Compiler environments, working closely with circuit designers to optimize performance, area efficiency, noise isolation, and reliability constraints. Focused on delivering robust, high-quality silicon solutions in product-driven environments through technical ownership and disciplined layout practices.

Stackforce AI infers this person is a VLSI Analog Layout Engineer with expertise in high-performance semiconductor design.

Location: Bengaluru, Karnataka, India

Experience: 7 yrs 1 mo