Naga Manikanta Morla

DevOps Engineer

Hyderabad, Telangana, India3 yrs 11 mos experience
Highly Stable

Key Highlights

  • Expert in static verification and low-power design.
  • Contributed to Synopsys' leading static products.
  • Awarded for academic excellence in engineering.
Stackforce AI infers this person is a Low-power Design and Static Verification Specialist in the EDA industry.

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Skills

Core Skills

Static VerificationLow-power Design

Other Skills

Logic SynthesisVerilogAssertion Based VerificationSystemVerilogSynopsys PrimetimeVC LPLower power design checksUnified Power Format (UPF)AMBA AHBTCLDigital LogicRTL DevelopmentTiming ClosureComputer Organisation and ArchitectureSynopsys Design Compiler

About

At Synopsys Inc, our team excels in delivering cutting-edge solutions for static verification challenges, including Linting, CDC, RDC, and Low Power Design Checks. With a BTech in Electronics and Communications from BML Munjal University, I've honed skills in RTL Design, Static verification, Low-power Design and Unified Power Format, contributing to the development of Synopsys' static products SpyGlass, VC SpyGlass, and VC LP. Acknowledged with the Academic Excellence Award for my scholarly achievements, I bring a rigorous analytical approach to troubleshooting and resolving RTL designers' issues. Our success in training customers and enhancing tool performance is a testament to our commitment to excellence in electronic design automation.

Experience

3 yrs 11 mos
Total Experience
3 yrs 11 mos
Average Tenure
3 yrs 11 mos
Current Experience

Synopsys inc

2 roles

Applications Engineering, Sr Engineer

Promoted

Dec 2024Present · 1 yr 6 mos · Hyderabad, Telangana, India · On-site

Applications Engineering, Engineer

Jul 2022Present · 3 yrs 11 mos · Hyderabad, Telangana, India · On-site

  • Works closely with RTL /ASIC designers and help them to perform static signoff. Technologies include Linting, Clock Domain Crossing (CDC), Reset Domain Crossing ( RDC) and Low Power Design Checks.
Logic SynthesisVerilogStatic verificationLow-power Design

Maven silicon

Technical Trainee

Mar 2022Jul 2022 · 4 mos · Bangalore

Assertion Based VerificationSystemVerilog

Education

BML Munjal University

Bachelor of Technology - BTech — Electronics and Communications Engineering

Jan 2018Jan 2022

FIITJEE

Intermediate — MPC

Jun 2016May 2018

RATNAM HIGH SCHOOL

X standard

Jul 2015Apr 2016

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