Saurav Gupta — Software Engineer
ASIC Digital Design Verification Engineer with 4+ years of experience focused on IP-level verification for USB/ eUSB2v2, Skilled in SystemVerilog, UVM (Universal Verification Methodology), Verdi, DVE, APB and AXI. Worked on functional coverage planning and closure, testbench development, assertions, regression debug and fixes, and constrained random verification.
Stackforce AI infers this person is a Digital Design Verification Engineer specializing in ASIC and VLSI technologies.
Location: Dhanbad, Jharkhand, India
Experience: 5 yrs 8 mos
Career Highlights
- 4+ years in ASIC Digital Design Verification.
- Expertise in SystemVerilog and UVM methodologies.
- Focused on IP-level verification for USB/eUSB2v2.
Work Experience
Synopsys Inc
ASIC Digital Design Sr Engineer (2 yrs 5 mos)
ASIC Digital Design Engineer (1 yr 7 mos)
Technical Intern (5 mos)
Team AVEON Racing
Vice Captain (9 mos)
Team Aveon Racing
Joint Secretary (10 mos)
Electrical & Electronics Engineering Society (EEESoc), BIT Mesra
Alumni Relations Coordinator (1 yr 8 mos)
Education
Bachelor of Technology - BTech at BIT Mesra Student-Industry Relations Cell