Nitesh M S

Director of Engineering

Bengaluru, Karnataka, India6 yrs 5 mos experience
Highly Stable

Key Highlights

  • Experienced in ASIC digital design and verification.
  • Proficient in multiple programming languages including Verilog and C++.
  • Strong background in timing analysis and system design methodologies.
Stackforce AI infers this person is a Digital Design Engineer with expertise in ASIC and embedded systems.

Contact

LinkedIn

Skills

Other Skills

Static Timing AnalysisRTL DesignVerilogC++C (Programming Language)ArduinoSMPSSystemVerilogInternet of Things (IoT)Application-Specific Integrated Circuits (ASIC)CDCSynopsys toolsdesign compilergcaSpyglass

Experience

6 yrs 5 mos
Total Experience
6 yrs 5 mos
Average Tenure
6 yrs 5 mos
Current Experience

Synopsys inc

4 roles

Supervisor II

Jan 2024 – Present · 2 yrs 5 mos

ASIC Digital Design Engineer II

Promoted

Mar 2022 – Jan 2024 · 1 yr 10 mos

ASIC Digital Design Engineer

Oct 2020 – Mar 2022 · 1 yr 5 mos

Technical Intern

Jan 2020 – Oct 2020 · 9 mos

Cisma consultants pvt ltd (a wholly owned subsidiary of verikwest systems inc, usa)

Internship Trainee

Jul 2019 – Jul 2019 · 0 mo · Bengaluru Area, India

  • Attended the skill development training on verilog

C-dot centre for development of telematics

Intern

Jun 2018 – Jul 2018 · 1 mo · Bengaluru Area, India

  • Worked on Linear mode power supply and SMPS methodologies

Education

Birla Institute of Technology and Science, Pilani

Master of Technology — Electrical and Electronics Engineering

Jan 2022 – Jan 2024

B. M. S. College of Engineering

Bachelor of Engineering

Jan 2016 – Jan 2020

SBM Jain College VVpuram

PUC — PCME

Stackforce found 100+ more professionals with Static Timing Analysis & RTL Design

Explore similar profiles based on matching skills and experience

RS

ROBIN SINGH

Sr. Product Validation Engineer

at Synopsys Inc

Delhi, India4 yrs 8 mos exp
VC SpyGlassCDC
VR

Vinay Reddy

Accumulated Expertise

at Career-Wide Experience

Hyderabad, India0 mo exp
MK

MD Kashif Khan

Project Fellow

at NIT Raipur

Bhilai, India9 mos exp
FPGAAnalog Mixed Signal
PT

Peddinti Twihal

Senior Engineer

at Micron Technology

Hyderabad, India3 yrs 11 mos exp
Very-Large-Scale Integration (VLSI)Static Timing AnalysisSTD CELLS
AM

Aman Mishra

ASIC Digital Design, Staff Engineer

at Synopsys Inc

Noida, India5 yrs exp
RTL DesignFront end toolflowsArea and Timing analysis of complex designs
NM

Naga Viswanath Muktagucha

Senior Engineer- Memory circuit design

at Micron Technology

Hyderabad, India4 yrs 2 mos exp
Universal Verification Methodology (UVM)SystemVerilogPython (Programming Language)
SK

Swastika Kumari

Senior Verification Engineer

at Ampere

Bengaluru, India9 yrs 9 mos exp
Verification EngineeringC++
SM

Sana Mazhar

Staff Engineer

at Qualcomm

Chennai, India9 yrs 7 mos exp
System on a Chip (SoC)