Naga Viswanath Muktagucha

Software Engineer

Hyderabad, Telangana, India4 yrs 2 mos experience

Key Highlights

Expert in RTL development and verification methodologies.
Proficient in Python scripting for automation and analysis.
Strong background in semiconductor design and verification.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in RTL development and verification.

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Skills

Core Skills

Universal Verification Methodology (uvm)SystemverilogPython (programming Language)

Other Skills

pandasSTA AnalysisHTMLSHELL scriptingVerilogCadenceDigital DesignsDigital Circuit DesignCMOSMixed SignalIntegrated Circuits (IC)ScriptingRTL Development

About

#RTL development #verilog #spyglass #perl • knowledge about digital design flow. • Understanding in Verilog RTL development and Perl scripting language. • basic knowledge of Synopsys based Spyglass Linting tools for CDC checks. • worked on tools like Cadence Virtuoso & simvision, Xilinx VIVADO. • basics of PYTHON, C-language.

Experience

4 yrs 2 mos

Total Experience

Average Tenure

Current Experience

Micron technology

Senior Engineer- Memory circuit design

Apr 2024 – Present · 2 yrs 2 mos · Hyderabad, Telangana, India · On-site

Synopsys inc

3 roles

Senior Application Engineer

Dec 2023 – Apr 2024 · 4 mos

Application Engineer

Promoted

Apr 2022 – Dec 2023 · 1 yr 8 mos

1. Direct Port Access - Design and Verification; Responsible for Development of new designs and verification environments based on the feature added or supported in the SimXL (simulation
acceleration).
2. System Verilog Virtual interface feature enhancement; Responsible for validation of Virtual interface (A new feature access of Enum variables using virtual interface).
3. Design Frequency Monitoring; • Responsible for multiple bugs uncovering during this tenure. with the design team to correct defects and test issues.
4. Bringing up of ZS6 Hardware; Created auto regression analysis mechanism, + JIRA filing mechanism, which reduced TAT from weeks to hours.
5. DDR5 Protocol and AMS Verification; • Responisble for creating RNM model for ADC, and many other analog circuits, to make them synthesizable in FPGA environment.

Universal Verification Methodology (UVM)SystemVerilog

Contractor

Feb 2022 – Apr 2022 · 2 mos

Responsible for Tracking/Monitoring the performance of the tool such as
total compile time and the operating frequency for the same design using
different versions.
Debugging the cause of the frequency drop and reporting the issue. Using
STA Analysis. (but the design will be partitioned across multiple FPGA)
Responsible for tuning Benchmark designs to improve performance of design. by, analysis of RTL code and changes in setup.
Responsible for creating automation, using PYTHON, HTML, SHELL scripting to reduce the time spent on report generation and basic information
for Analysis. (Reduced 40hrs work each week)

Python (Programming Language)pandas