V

Vinay Reddy

CEO

Hyderabad, Telangana, India0 mo experience

Key Highlights

  • Trained in RTL Design Verification methodologies.
  • Proficient in Verilog and SystemVerilog.
  • Knowledgeable in VLSI design and verification.
Stackforce AI infers this person is a VLSI Design Verification Engineer.

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Skills

Other Skills

Open Verification MethodologyCode CoveragePCIeCommunicationUniversal Verification Methodology (UVM)VerilogSystemVerilogRTL DesignRTL VerificationVery-Large-Scale Integration (VLSI)

Education

Vignan Institute of Technology and Science

Bachelor of Technology - BTech — Electronics and instrumentation engineering

Apr 2018Apr 2021

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