Reddy Nayak Vaditya

CEO

Bengaluru, Karnataka, India8 yrs 9 mos experience

Highly StableAI Enabled

Key Highlights

8+ years in SoC emulation and validation
Proven expertise in RTL-to-bitfile flows
Holds a patent in Digital Pre-distortion technology

Stackforce AI infers this person is a Semiconductor and Telecommunications expert with strong capabilities in hardware emulation and digital design.

Contact

Skills

Core Skills

Hardware EmulationSystem On A Chip (soc)PrototypingDigital Designs

Other Skills

TCLPython (Programming Language)VerilogMATLABArtificial Intelligence (AI)Edge AIMachine LearningVeloceXilinxCC++Wireless Communications SystemsField-Programmable Gate Arrays (FPGA)ProgrammingTest Planning

About

Senior Lead VLSI Engineer with 8+ years of experience in SoC emulation, system-level validation, and FPGA prototyping, with strong expertise in SoC architecture, internal interconnects, and high-speed interface integration. Proven track record in RTL-to-bitfile flows, SPNR analysis, and TCL/Python automation across Qualcomm, Synopsys, and BEL. Actively exploring AI-assisted methodologies for hardware debug and emulation productivity. Holds an approved patent in Digital Pre-distortion (DPD).

Experience

8 yrs 9 mos

Total Experience

3 yrs 4 mos

Average Tenure

2 yrs

Current Experience

Qualcomm

Senior Lead Engineer

Jun 2024 – Present · 2 yrs · Bengaluru, Karnataka, India · On-site

As an Emulation Engineer, I drive end-to-end SoC emulation on multi-FPGA platforms, contributing to the delivery of multiple Qualcomm SoCs on in-house RUMI platforms.
I own SoC-level integration and emulation build generation using Siemens Veloce, including RTL stitching, configuration, and build readiness, and support multiple subsystems such as wireless processing blocks, peripherals, and the Turing subsystem, managing the flow from RTL handoff to timing-closed FPGA bitfile generation.
I perform system-level debug and failure root-cause analysis using waveform and signal-dump debugging, and validate builds using T32 debugger and CMM scripts to ensure functional correctness and software readiness. My work involves resolving complex multi-domain SoC issues spanning memory, clocking, power (RSC), AHB/APB protocols, NoC, peripherals, and debug infrastructure.
I have a strong understanding of SoC architecture and internal connectivity, including interconnect fabric, protocol-based integration, and external interfaces such as PCIe and UFS, with hands-on exposure to DDR memory subsystem integration and system-level bring-up.
To improve productivity, I developed TCL-based automation and an AI-assisted emulation log analysis pipeline integrating Veloce logs with internal LLM-based reasoning. Along with technical ownership, I actively mentor engineers and conduct team trainings on SoC timing concepts, build-generation practices, and advanced debug methodologies.

Hardware EmulationSystem on a Chip (SoC)TCLPython (Programming Language)

Synopsys inc

Senior Application Engineer 1

Dec 2022 – Jun 2024 · 1 yr 6 mos · Bengaluru, Karnataka, India · On-site

As a Product Validation Engineer, I am responsible for validating various prototyping features within the Protocompiler tool. I create comprehensive test plans and test cases essential for prototyping feature validation. I have been involved in prototyping various designs from NVIDIA and APPLE on the latest platform, HAPS200. Additionally, I work on updating regression suite test cases to reflect the latest changes. I have developed multiple automation frameworks using Python for data extraction from prototyping log files, as well as TCL scripts to automate the prototyping flow.

TCLPython (Programming Language)Prototyping

Bharat electronics

Member Research Staff

Sep 2017 – Dec 2022 · 5 yrs 3 mos · India · On-site

During my tenure at BEL-CRL, I led projects focused on the design and development of advanced FPGA and RTL solutions. One of my key projects was the Adaptive Digital Predistortion (DPD) for RF Power Amplifiers, where I developed a robust algorithm to correct non-linearities, significantly enhancing amplifier performance and efficiency. I utilized Indirect Learning Architecture and Least-square Solutions for precise inverse system estimation, leveraging MATLAB for algorithmic design. The DPD was implemented in Verilog HDL for execution on Xilinx FPGAs, with successful deployment on the ZC706 Xilinx Evaluation Board and FMCOMMS5 (AD9361 RF transceiver) hardware. Using Vivado, I generated RTL to bit file conversion and integrated the algorithm with in-house 16-QAM modem RTL to verify functionality across power levels, achieving a 10-15 dB reduction in adjacent channel power and a 5-7% improvement in Error Vector Magnitude (EVM).
I also worked on the RTL Development of OFDM Waveforms, integrating Peak-to-Average Power Ratio (PAPR) reduction techniques. I designed transmitter and receiver waveforms using OFDM technology in MATLAB and implemented them in RTL with Verilog HDL. The complete design was ported onto the ZC706 Xilinx Evaluation Board and FMCOMMS5 hardware for verification. I established PS and PL communication for adaptive threshold limiting and integrated JPerf communication to test throughput, ensuring robust performance with a 2KW Power Amplifier. My efforts led to the successful implementation of a comprehensive end-to-end testbed.
Got the experience in RTL design for wireless modem systems and verification.

VerilogDigital DesignsMATLAB