Ranjitha C L — Software Engineer
Stackforce AI infers this person is a VLSI Design Engineer with expertise in Analog Layout and Physical Verification.
Location: Bengaluru, Karnataka, India
Experience: 3 yrs
Skills
- Analog Layout
- Very-large-scale Integration (vlsi)
Career Highlights
- Experienced in Analog Layout Design and VLSI.
- Proficient in using Synopsys and Cadence tools.
- Strong foundation in Verilog-AMS and Physical Verification.
Work Experience
Synopsys Inc
Analog Layout Design Sr Engineer (1 yr 4 mos)
A&MS Layout Design engineer1 (1 yr 8 mos)
A&MS layout design intern (7 mos)
Education
Bachelor of Engineering - BE at RNS Institute of Technology - India
Master of Technology - vlsi and microelectronics at BITS Pilani Work Integrated Learning Programmes
