Hemanth kumar Yadav — Software Engineer

DFT Engineer, worked on ATPG DRC & Pattern generation, coverage analysis and improvement, pattern validation for different fault models. SKILLS SOC Flow, DFT Basic and fundamentals, SCAN Architecture, SCAN DRC, SCAN Insertion, Compression Insertion, Boundary Scan, JTAG, ATPG Faults, Fault models, ATPG Coverage, ATPG for Stuck-at and Transition fault models and Pattern simulations. Post Silicon Testing of DFX features for high speed IOs. Architect, Design & Validate these test features with a robust & scalable test plan development at unit-level and SOC/Full Chip level using verification methodologies like UVM and Tessant Internal tools. Pre-Silicon Simulation and Debug of Test functionality using standard Industry tools and sign off on Test coverage for various products using standard coverage metrics. Ability to work on automation, flow development & improvement, coverage metrics, test execution, bug identification/fix and IO-test productization. Solve complex Test problems in the mixed-signal world and develop a scalable test solution that works across platforms. Work with powerful Industry-standard tools for Design and verification methodologies. This includes SV, UVM, Perl, Python and custom tools/flows. Partnering closely with our IP teams for design/verification of IOBIST test-logic, Collaborating with Mixed Signal Circuit design teams to understand the analogue design components in an IO cell. Collaborate with other DFX teams, coordinate with Post Silicon Test Engineering and Production Engineering teams for productizing quality test at efficient test cost. Professional Experience: MBIST • Created custom algorithms to identify the faults for SLT rejected dies. • Worked on defining methodologies and implementing DFT architecture for SoCs. • Inserted MBIST logic at Block and Top level. • Methodologies changes into MBIST architecture to reduce TestTime with higher Tckspeedup. • Responsible for simulations at different stages(BTO/MTO) for both timing/Zero delay on both RTL and Gate level. SCAN • Worked on defining methodologies and implementing DFT architecture for SoC’s. • Generated pinmux logic for different test modes. • Resolved issues related to vmin and fmax and shmoo holes. ATPG • Generation of test patterns which includes, compressed patterns and At-Speed vectors. • Identified and analyzed areas of low fault coverage and suggested mechanisms to increase coverage. IJTAG • Ijtag implementation for controlling blocks with SIB. • Development of ICL and PDL according to the test case. • Bscan implementation and verification for SoC level.

Stackforce AI infers this person is a Semiconductor Testing Expert with strong DFT and automation skills.

Location: Hyderabad, Telangana, India

Experience: 13 yrs