muddam Venkata Ganesh

Software Engineer

Andhra Pradesh, India3 yrs 3 mos experience

Highly Stable

Key Highlights

Expert in Design Verification with 3 years at Intel projects.
Proficient in UVM and SystemVerilog for complex semiconductor designs.
Strong debugging skills with a focus on root cause analysis.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in Design and Functional Verification.

Contact

muddamvenkatganesh@gmail.com LinkedIn

Skills

Core Skills

Design VerificationFunctional Verification

Other Skills

SystemVerilogUVMVerilogRegression TestingDebuggingTest CoverageEthernetShell ScriptingPythonPerlTest ExecutionElectronic EngineeringComputer LiteracyProficiency TestingXilinx ISE

About

I have spent the last 3 years doing design verification on Intel semiconductor projects — Ethernet IP, NoC switch routing, and SOC-level work — at Tech Mahindra. Most of my time has been in the trenches: writing UVM testbenches, closing functional coverage, running regressions, and debugging failures through waveforms and log files at 11pm when a sanity run breaks. I work in SystemVerilog and UVM. My go-to tools are Synopsys VCS and QuestaSim. I have worked with AHB, APB, and Ethernet (IEEE 802.3) protocols. I write scripts in Shell, Python, and Perl to automate regression runs and reporting so the team is not doing it manually every day. What I enjoy most is the debugging side — finding why a test failed, tracing it back to the root cause, and fixing it properly rather than just masking it. I am currently looking for Design Verification Engineer roles in Bengaluru or remote. If you are hiring or know someone who is, feel free to reach out.

Experience

3 yrs 3 mos

Total Experience

3 yrs 2 mos

Average Tenure

Current Experience

Tech mahindra cerium systems

Design Verification Engineer

Mar 2022 – Apr 2025 · 3 yrs 1 mo · Bangalore Urban, Karnataka, India · On-site

Ethernet IP Verification — PSG_PIPE_ETH_IP_COE
Client: Intel India · Dec 2023 – Apr 2025
High-speed 400G/100G Ethernet IP verification. Worked on IP-level RTL verification of components like alt_ehipc3, mdio, ultra_25_f, and e25s10. Ran regression suites, tracked bugs in HSD, validated 100+ testcases in SPETC, and did detailed error analysis on failing IP and regtest paths.
SOC Verification Support — AXG_SOC_EMU
Client: Intel India · Mar 2023 – Nov 2023
Verification support role on an emulation-based SOC project. Executed sanity testcases using the AXE tool, analysed waveforms and log files to debug functional failures, and helped develop constraint-based corner-case testcases.
NoC Switch IP Verification — XEG_EMR_GNRC_PCOE
Client: Intel India · Mar 2022 – Feb 2023
Network-on-Chip packet routing IP verification for Intel EMR platform. Built UVM testcases for packet routing through NoC switches, drove functional coverage closure using covergroups, injected error scenarios for negative testing, and automated daily regression runs with email reporting.

SystemVerilogUVMVerilogRegression TestingDebuggingFunctional Verification+6

Tech mahindra pvt. ltd (formerly cerium systems)

Design Verification Engineer

Dec 2021 – Apr 2025 · 3 yrs 4 mos

3 years of hands-on RTL verification and UVM testbench development experience across 3 Intel semiconductor projects at IP and SOC level. Completed 4 months of internal Design Verification training at Tech Mahindra (Dec 2021 – Mar 2022) covering SystemVerilog, UVM methodology, and simulation tools before project deployment.

SystemVerilogUVMVerilogDesign VerificationFunctional Verification