Rupam Banik

Software Engineer

Gyeonggi, South Korea2 yrs 11 mos experience

Most Likely To Switch

Key Highlights

Expert in Static Timing Analysis and DFT.
Proven track record in VLSI and Digital IC Design.
Awarded for driving positive change in projects.

Stackforce AI infers this person is a Semiconductor Engineer with expertise in VLSI and Digital IC Design.

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Skills

Core Skills

Static Timing AnalysisVery-large-scale Integration (vlsi)DftDigital Ic Design

Other Skills

PrimeTimePrimeClosureECOSpice Vs Library CharacterizationTCL scriptingSynopsys Prime TimeXilinx VivadoVerilogPresentation SkillsAnalog Circuit DesignTCLTimingTessentDebuggingTiming Closure

Experience

2 yrs 11 mos

Total Experience

1 yr 5 mos

Average Tenure

2 yrs 7 mos

Current Experience

Synopsys inc

Sr Application Engineer

Nov 2023 – Present · 2 yrs 7 mos · Gyeonggi, South Korea

Static Timing Analysis, PrimeTime, PrimeClosure, ECO, Spice Vs Library Characterization. Experience with Samsung latest 2nm/3nm Technology Nodes.

Static Timing AnalysisPrimeTimePrimeClosureECOSpice Vs Library CharacterizationVery-Large-Scale Integration (VLSI)

Indian institute of information technology design & manufacturing kancheepuram

2 roles

Digital Neuromorphic Circuits

Promoted

May 2022 – Sep 2022 · 4 mos · India

Digital Implementation in Verilog
Implementation of Neuron Learning rules Pair based and Triplet based Spike Timing Dependent Plasticity along with frequency based classification through BCM model for real-time ECG signal analysis.
Implemented Izikiveich Neuron Model.

Xilinx VivadoStatic Timing AnalysisVerilogDigital IC Design

Half Time Teaching Assistant

Sep 2021 – Apr 2022 · 7 mos · India

Static Timing AnalysisPresentation Skills

Amd

Co-op Engineer

May 2022 – May 2023 · 1 yr · Bengaluru, Karnataka, India · On-site

Worked extensively on DFT timing. Performed Special timing checks on clock observe path, scan channel skew checks and other timing checks for efficient timing closure in project. Worked with senior colleagues in understanding Shift and Func constraints from DFT perspective. Worked on Scan Path Checking, Non scan-No clock comparisons after every milestone. Worked on CDC checks.
Had brief experience in ATPG flow for Silicon Bring Up.
Good Experience on TCL scripting for enabling automation. Good experience on Synopsys Prime Time tool and it's commands. Also enabled automation in Synopsys Prime Time through TCL scripting.
Received Spotlight Award for driving positive change and making significant contribution towards ongoing project.

Static Timing AnalysisDFTTCL scriptingSynopsys Prime Time