Tanmay Chakravorty — Software Engineer

Analog / Mixed-Signal IC Design Engineer with industry experience on advanced-node high-speed I/O programs, including PCIe4 and PCIe6 SerDes. Experienced on PLL subsystems and clocking paths in 2nm and 4nm technologies, with hands-on ownership of pre-scaler SCM clocking and external clock injection architectures. Experienced in designing and verifying analog and mixed-signal blocks such as PLL charge pumps, bandgap references, comparators. Strong focus on clock quality and receiver metrics including rise/fall time, random and deterministic jitter (RJ/DJ), CMRR, gain/attenuation vs frequency, input impedance, and VCM settling behavior. Comfortable with sign-off style verification, including PVT corner analysis, Monte Carlo mismatch, aging, EM/IR, noise, jitter, AC, and transient simulations. Proficient with industry-standard EDA tools such as Cadence Virtuoso/MAESTRO and Synopsys Custom Compiler/PrimeWave, across process nodes ranging from 180nm and 130nm to advanced 45nm, 28nm, 4nm, and 2nm. Currently pursuing an MSc in Electrical Engineering (RF IC Design) at TU Eindhoven. Actively interested in analog, mixed-signal, PLL, and high-speed I/O design roles where rigorous circuit analysis, architecture trade-offs, and silicon-proven verification practices are valued.

Stackforce AI infers this person is a Mixed-Signal IC Design Engineer with expertise in high-speed I/O and PLL subsystems.

Experience: 2 yrs 2 mos