Akash Singh — CTO
SoC Design Engineer at STMicroelectronics, working on RTL front-end flows for next-generation silicon. Focused on architecting and integrating IPs to hit PPA targets the first time — across micro-architecture, RTL Integration, Lint, CDC, STA, and Low-power design checks (UPF). Soft spot for solving the elusive cross-IP bugs that surface late in the cycle. Off the clock: biking, photography, and cricket — because work - life balance matters as much as tapeouts.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in RTL and ASIC development.
Location: Varanasi, Uttar Pradesh, India
Experience: 4 yrs 1 mo
Skills
- Asic Design
- Rtl Integration
- Rtl Development
- Formal Verification
Career Highlights
- Expert in RTL front-end flows for next-gen silicon.
- Proficient in architecting and integrating IPs for optimal PPA.
- Strong problem-solver for cross-IP bugs in design cycles.
Work Experience
STMicroelectronics
Technical Leader (1 mo)
7Rays Semiconductors
Senior RTL Design Engineer - IP/SoC (2 mos)
Synopsys Inc
Senior Engineer (2 yrs)
Applications Engineer II (2 yrs 1 mo)
Maven Silicon
Student Intern (Advanced VLSI Design & Verification) (1 yr)
Uttar Pradesh Power Corporation ( Uppcl )
Summer Trainee (1 mo)
Education
Master of Technology - MTech at Birla Institute of Technology, Mesra
Bachelor of Technology - BTech at Raj Kumar Goel Institute of Technology, Ghaziabad
CLASS XII at Seth M. R. Jaipuria School Lucknow