Shirsendu Acharyya

Product Engineer

Hyderabad, Telangana, India1 yr 11 mos experience

Key Highlights

Expert in FPGA Microarchitecture and System Design.
Proficient in RTL Development and Hardware-Software Integration.
Strong background in Digital Signal Processing and Real-Time Systems.

Stackforce AI infers this person is a Telecommunications and Aerospace VLSI Engineer with expertise in FPGA and DSP systems.

Contact

Skills

Core Skills

Microarchitecture DesignSystem DesignDigital Signal ProcessingRtl Development

Other Skills

PS–PL IntegrationStatic Timing Analysis (RTL)FPGA-based system designHardware-software integrationFilter Bank DesignMultirate Signal ProcessingStatic Timing AnalysisReal-Time SystemsEvent SchedulingHardware ValidationC++JSON ParsingMATLABXilinx FpgaDSP Architecture

About

I am an VLSI Engineer working on FPGA Microarchitecture system design and hardware-software integration. My experience includes RTL development, microarchitecture design, and PS-side C/C++ programming on Zynq/RFSoC platforms. I have worked on signal processing pipelines, communication system data paths, and real-time scheduling and control systems, with a focus on building complete and scalable designs. I am interested in roles that involve system design, microarchitecture, and end-to-end FPGA/ASIC development, where I can contribute to solving real engineering problems and building efficient hardware systems.

Experience

1 yr 11 mos

Total Experience

Average Tenure

Current Experience

Signion systems

2 roles

VLSI Engineer

Jul 2024 – Present · 1 yr 11 mos · On-site

Working on FPGA-based system design, microarchitecture development, and PS–PL integration.
Designed and implemented a wideband signal processing pipeline using filter bank architecture for frequency decomposition.
Worked on microarchitecture and RTL for a beam processing data path enabling flexible bandwidth allocation and end-to-end uplink/downlink handling in a communication payload
Built real-time scheduling and playback system including Real Time Click with 100 nanosecond precision, event scheduler, and waveform control logic for time-critical operations
Designed and implemented a beacon signal generation system with PS-side control and PL-based playback, validated on hardware for satellite tracking use cases
Developed a ground-to-satellite contact management system using C++, including JSON-based configuration parsing and real-time scheduling under hardware constraints
Worked across MATLAB modeling, RTL implementation, and hardware validation to ensure system-level correctness

PS–PL IntegrationStatic Timing Analysis (RTL)Microarchitecture DesignSystem DesignFPGA-based system designHardware-software integration

RTL Design Intern

Aug 2023 – Jul 2024 · 11 mos · On-site

Digital Signal Processing || ZCU111 RF SoC FPGA implementations || DSP48E2 || Clock Change RAM and Asynchronous FIFO design (CDC Handling) || Polyphase Semi parallel FIR Filter Bank Architecture Design || Divide and Conquer Approach to implement 48 length IFFT Architecture || Beam Spectral Verification in MATLAB || AXI Bus protocol || Clock Path Optimization || Data Path Optimization || Memory Optimisation || AXI Memory Mapping || FSM logic ||

MATLABXilinx FpgaDigital Signal ProcessingDSP ArchitectureClock Domain Crossing (RTL)RTL Synthesis+1