H

Himanshu Kumar

Software Engineer

Palamu, Jharkhand, India3 yrs 9 mos experience

Key Highlights

  • Expert in SystemVerilog and UVM for scalable verification.
  • Hands-on experience with Synopsys ZeBu emulation.
  • Strong debugging skills with VCS and Verdi.
Stackforce AI infers this person is a Verification Engineer in the EDA industry.

Contact

Skills

Core Skills

EdaSystemverilogUvm

Other Skills

TCLUniversal Verification Methodology (UVM)Regression TestingRAL modelUnified Power Format (UPF)EmulationZebuPython (Programming Language)BashSynopsys toolsVcsSynopsisCadence VirtuosoVerilogDigital System Design

About

Design Verification Engineer @ Synopsys | UVM | SystemVerilog | Zebu Emulation | AXI/APB | Debug & Bring-up a.) Currently working at Synopsys on PVT Controller (PVTC) verification across advanced nodes (2nm, 3nm). b.) Strong expertise in SystemVerilog, UVM, and building scalable verification environments. c.) Hands-on experience with Synopsys ZeBu emulation, including regression acceleration and debug. d.) Strong debugging skills using VCS, Verdi, waveform analysis, and SVA. e.)Experience in scripting (TCL, Python, Bash) for automation and productivity improvement.

Experience

3 yrs 9 mos
Total Experience
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Average Tenure
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Current Experience

Synopsys inc

Research And Development Engineer 1

Jul 2023Present · 2 yrs 11 mos · Bhubaneswar · On-site

EDATCL

Asiczen technologies

2 roles

Digital Design Engineer

Apr 2023Jul 2023 · 3 mos · Bhubaneswar, Odisha, India

SystemVerilogUniversal Verification Methodology (UVM)UVM

Digital Design Engineer

Sep 2022Jul 2023 · 10 mos · Bhubaneswar, Odisha, India

Education

BITS Pilani Work Integrated Learning Programmes

Master of Technology - MTech — Vlsi and microelectronics

Jul 2025Aug 2027

NIST University

Bachelor's degree — Electronic and Communications Engineering

Aug 2019Aug 2023

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