aadil amoura , PhD

CTO

Grenoble, Auvergne-Rhône-Alpes, France27 yrs 1 mo experience

Key Highlights

Over 25 years of expertise in logic synthesis and physical synthesis.
Invented state reachability engine, achieving up to 90% area savings.
Strong leadership in building high-performing technical teams.

Stackforce AI infers this person is a Microelectronics expert with a focus on logic and physical synthesis.

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Skills

Core Skills

Logic SynthesisPhysical SynthesisLogic Design

Other Skills

C++Power OptimizationSequential OptimizationDelay OptimizationSequential mappingClock gatingMultibitGitHubCursor AIVHDLProject ManagementPeople ManagementLeadershipGraph TheoryEDA

About

With over 25 years of experience, I specialize in logic synthesis, physical synthesis, and large-scale hardware/software co-design, along with optimization algorithms. I have developed innovative solutions in areas such as state reachability (Concurrent constant registers removal and equal-opposite registers merging), power optimization (including clock gating and logic restructuring/relocation for improved power efficiency), sequential optimization, delay optimization engines, multibit banking/debanking, and area-driven techniques, delivering strong results across multiple tools. I have served as both a technical leader and an individual contributor for more than 25 years, while also working in parallel as a manager for over 5 years. I have collaborated closely with cross-functional teams, successfully hiring, mentoring, and growing high-performing teams. I value open technical dialogue and maintain a strong commitment to intellectual honesty. Core strengths: • Deep expertise in RTL and physical synthesis • Strong problem modeling and analytical skills, with a proven track record of delivering complex projects on time and with high quality • Solid foundation in mathematics and operations research • Extensive experience in microelectronics and EDA • Software development across the full lifecycle: requirements, specifications, architecture, and delivery • Leadership and management: technical leadership, inclusive people management, and effective product and project planning

Experience

27 yrs 1 mo

Total Experience

Average Tenure

Current Experience

Synopsys inc

Senior Architect Engineer

Nov 2000 – Present · 25 yrs 7 mos · Montbonnot Saint Martin France

I am a member of the Design Compiler and Fusion Compiler teams, contributing across multiple key domains:
Logic Synthesis:
Invented and developed the state reachability engine that enables concurrent constant register removal and merging of equivalent and opposite registers. This innovation delivered significant area savings, achieving up to 90% reduction in some designs.
Implemented advanced sequential mapping and state analysis techniques to improve overall design quality.
Worked extensively on delay optimization and leakage power reduction.
Designed and implemented multiple register optimizations, including timing-driven register duplication, phase-inverted transformations, fast NPN transformations, and both standard and advanced shift register identification and optimization.
Delivered several innovations in incremental placement, high-fanout synthesis, sizing, and logic restructuring to improve area, timing, and power.
Enhanced PPA and runtime of the timing optimization engine by implementing dominant‑gate selection heuristics.
Consistently ranked among the top contributors to tool MBOs, at times achieving more than 70% of the team’s annual goals.
Physical Synthesis:
Contributed to path adjustment and incremental placement using path-smoothing techniques.
Developed innovative approaches for clock-gate relocation to improve power efficiency.
Delivered optimization solutions for timing, congestion, power, and area.
Design for Test (DFT):
Developed and implemented a new scan insertion algorithm in Design Compiler, enabling direct mapping from RTL to scan cells.
Core Infrastructure and Optimization Engines:
Implemented high-performance incremental placement algorithms.
Developed multiple engines delivering strong PPA improvements across sequential optimization, multibit optimization, and power, area, and timing optimization.
I am recognized as a domain expert across multiple areas of logic and physical synthesis.