Dara Rama Krishna

Software Engineer

Bangalore Urban, Karnataka, India5 yrs experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Technical enthusiast with a strong background in ECE.
  • Achieved Gate Rank 3000, showcasing competitive excellence.
  • Experienced in application engineering at Synopsys.
Stackforce AI infers this person is a VLSI design engineer with expertise in application engineering for semiconductor tools.

Contact

LinkedIn

Skills

Core Skills

Synopsys Design Compiler

Other Skills

FormalitySynopsys PrimetimePrime timeRTLASynopsys FormalityFusion compilerLogic DesignPhysical DesignFloorplanningStatic Timing AnalysisPlace & RouteClock Tree SynthesisPerlDesign Rule Checking (DRC)Tcl-Tk

About

I am technical enthusiast......Got Gate Rank 3000.Interested in Sharing the knowledge of technical stuff(ECE).

Experience

5 yrs
Total Experience
2 yrs 6 mos
Average Tenure
4 yrs 1 mo
Current Experience

Synopsys inc

2 roles

Staff Application Engineer

Feb 2025 – Present · 1 yr 4 mos

Senior Application Engineer

May 2022 – Present · 4 yrs 1 mo

Synopsys Design CompilerFormality

Ust

Physical Design Engineer

Jun 2021 – Jun 2022 · 1 yr · Bangalore Urban, Karnataka, India

Rv-vlsi vlsi and embedded systems design center

Physical design trainee at RV-VLSI

Mar 2021 – Sep 2021 · 6 mos · Bangalore Urban, Karnataka, India

Education

Sri Venkateswara University

Master of Technology - MTech — signal processing

Jan 2016 – Jan 2018

G. Pulla Reddy Engineering College

Bachelor of Technology - BTech — ECE

Oct 2011 – Jan 2015

Stackforce found 100+ more professionals with Synopsys Design Compiler

Explore similar profiles based on matching skills and experience

CM

Carrie Marwein

Senior Design Engineer

at GlobalFoundries

Noida, India3 yrs 4 mos exp
Memory DesignSRAM Architecture
SS

Sai Sandhya K

Physical Design Engineer

at Synapse Design Inc.

Bengaluru, India0 mo exp
YJ

Yadukrishnan J

Research And Development Engineer

at Synopsys Inc

Ernakulam, India4 yrs 10 mos exp
CC++PythonVery-Large-Scale Integration (VLSI)
JY

Jaswanth kumar yadlapalli

Sr.Layout engineer

at Synopsys Inc

Vijayawada West, India5 yrs 7 mos exp
IC LayoutPhysical VerificationAnalog Layout
AV

Aishwariya Vidhyasegar

CPU Physical Design Engineer

at Intel Corporation

Austin, United States3 yrs 11 mos exp
CDC design checkHigh Voltage audit
Sreesurya Aitha

Sreesurya Aitha

Architecture DV Intern

at Tenstorrent

San Francisco, United States5 yrs 10 mos exp
Computer ArchitectureVerification and Validation (V&V)LeadershipDigital logic design
Akhil Reddy P

Akhil Reddy P

Physical Design Engineer

at Qualcomm

Austin, United States1 yr exp
Physical Design
Aswini K P

Aswini K P

Hw-assisted Verification | Staff Engineer

at Synopsys Inc

Bengaluru, India7 yrs 6 mos exp
Static Timing AnalysisRTL DesignPhysical DesignPower Optimization