Bala Murali Krishna Baisani — Software Engineer
Design Verification Engineer with 3+ years of experience in SystemVerilog and UVM. Contributed to Ethernet MAC IP verification with focus on register testing (RAL), assertion development, and debugging. Experienced in achieving functional and code coverage closure. Also familiar with AHB and APB protocols. Skilled in tools like Synopsys Verdi, VCS, and Questa, with a strong commitment to quality and thorough verification.
Stackforce AI infers this person is a VLSI Design Verification Engineer with a focus on Ethernet technologies.
Location: Bengaluru, Karnataka, India
Experience: 4 yrs 9 mos
Skills
- Ethernet
- Ethernet(mac Layer)
- Universal Verification Methodology (uvm)
Career Highlights
- 3+ years in Design Verification Engineering.
- Expertise in SystemVerilog and UVM methodologies.
- Proven track record in Ethernet MAC IP verification.
Work Experience
Juniper Networks
ASIC verification engineer 3 (11 mos)
Digicomm Semiconductor
Senior Design Verification Engineer (8 mos)
UST
Engineer - 1 (design verification engineer) (1 yr 11 mos)
Associate engineer - A2 (design verification engineer) (11 mos)
Associate engineer - A1( design verification engineer) (4 mos)
Maven Silicon
rtl design and verification trainee (7 mos)
CARE Hospitals, Quality CARE India Limited
Biomedical Technician apprentice (5 mos)
Education
BTech - Bachelor of Technology at Sri Venkateswara University
Special diploma in electronics (Bio-medical) at Government institute of electronics
ssc at Sri Sarawati vidhya mandir
