Sourav Das

Software Engineer

Bengaluru, Karnataka, India4 yrs 8 mos experience
Highly Stable

Key Highlights

  • Expert in formal verification and RTL design.
  • Proficient in SystemVerilog and Verilog.
  • Strong background in semiconductor design and verification.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in formal verification and RTL design.

Contact

Skills

Core Skills

Formal VerificationSystemverilogVerilog

Other Skills

LinuxGate Level SimulationChipSim VerificationRTL DesignDigital DesignsSpyglassMatlabC++C (Programming Language)Microsoft OfficeSVAUniversal Verification Methodology (UVM)MATLAB

About

Hardware Engineer skilled in SystemVerilog, Perl, C, C++ and Verilog

Experience

4 yrs 8 mos
Total Experience
4 yrs 8 mos
Average Tenure
--
Current Experience

Cisco

ASIC Engineer

Aug 2019Apr 2024 · 4 yrs 8 mos · Greater Bengaluru Area

  • Hands on experience in formal verification ( using VCFormal tool ).
  • Experience in Gate level simulations of complex design blocks with synthesizable netlist and postPD netlist ( with SDF).
  • Exposure in ChipSim verification (FullChip verification)
  • Recently working as RTL designer of CPU subsystem and bus slave peripherals.
LinuxFormal VerificationSystemVerilog

Education

Indian Institute of Technology, Kanpur

M.Tech

Jan 2017Jan 2019

Institute Of Engineering and Management

BTech - Bachelor of Technology — Electronics and communication engineering

Jan 2013Jan 2017

Nava Nalanda

Higher Secondary

Jan 1999Jan 2013

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