CHAND BADSHAH

Software Engineer

Bengaluru, Karnataka, India4 yrs experience
Highly Stable

Key Highlights

  • Senior Engineer with extensive ASIC design experience.
  • Proficient in VLSI and digital design methodologies.
  • Strong background in PCIe design and development.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and VLSI technologies.

Contact

LinkedIn

Skills

Other Skills

Very-Large-Scale Integration (VLSI)VerilogSystemVerilogstatic timingCadence VirtuosoLTSpiceXilinx VivadoC (Programming Language)Python (Programming Language)Application-Specific Integrated Circuits (ASIC)Digital cmos vlsi design

About

I am working as a ASIC Digital design Sr Engineer at Synopsys India Pvt Ltd .

Experience

4 yrs
Total Experience
3 yrs 7 mos
Average Tenure
5 mos
Current Experience

7rays semiconductors

Senior Engineer-RTL

Jan 2026 – Present · 5 mos · Bengaluru, Karnataka, India · On-site

Synopsys inc

2 roles

ASIC Digital Design Sr Engineer

Promoted

Feb 2024 – Jan 2026 · 1 yr 11 mos · Bengaluru, Karnataka, India · On-site

ASIC Digital design Engineer II

Jun 2022 – Feb 2024 · 1 yr 8 mos · Bengaluru, Karnataka, India · On-site

  • working in PCIe Design team.

Education

National Institute of Technology , Patna

Master of Technology - MTech — microelectronics &Vlsi design

Jan 2020 – Jan 2022

Faculty of Engineering and Technology, Jamia Millia Islamia

Bachelor of Engineering - BE — Electronics and Communications Engineering from JAMIA MILLIA ISLAMIA NEW DELHI

Jan 2016 – Jan 2020

Faculty of Engineering and Technology, Jamia Millia Islamia

Diploma in Engineering

Jan 2012 – Jan 2015

Hari Shankar Nayak high school

Mertriculation — PCM

Jan 2011 – Jan 2012

Stackforce found 100+ more professionals with Very-Large-Scale Integration (VLSI) & Verilog

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